Abstract: A capacitive liquid level sensor having phase detecting circuitry incorporates a capacitive sensor array, an oscillator generating an input signal, a switching circuit sequentially coupling the input signal to the input plates of the capacitive sensor, one at a time, a pair of phase lock loop circuits (PLLs) each having voltage controlled oscillators (VCOs), a second switching circuit selectively coupling the output plates of the capacitive sensor array, in sequential fashion, to the PLLs, and an exclusive OR-gate (XOR) receiving the outputs of the VCOs from each of the PLLs. The XOR generates a first logic level signal when a difference in the phase of two signals from any two adjacent output plates indicates that a phase difference is present. A second logic signal is generated if no phase difference is detected. The signals are perfectly in phase when any two adjacent output plates are either submerged in fluid or both disposed in air.