Abstract: A delay locked loop includes a delay circuit capable of generating an output clock and further capable of generating a GATE signal in response to an aliased condition. A phase detector is coupled to the delay circuit and is capable of comparing a phase difference between a reference clock and the output clock from the delay circuit and generating a pump up signal if the output clock is lagging the reference clock. The phase detector is capable of generating a pump down signal if the output clock is leading the reference clock. A charge pump is coupled to the phase detector and is capable of generating a control voltage for controlling the delay provided to the output clock and capable of pulling up the control voltage in response to the GATE signal.

Abstract: An output driver is provided with driving and filtering capability. An output current driver and output voltage driver embodiments are provided. The output current driver includes, an operational amplifier having a first input for receiving a first input voltage V1, a second input for receiving a second input voltage V2, and an output for generating an output voltage Vc. The output current driver also includes a transistor having an input terminal coupled to the output of the operational amplifier for receiving the output voltage Vc, a first terminal coupled to a differential pair, and a second terminal coupled to the second input of the operational amplifier, wherein an output current Iout flows across the transistor. A control current ICONTROL determines a value of the first input voltage V1, while the output voltage Vc controls the transistor so that the second voltage V2 becomes equal to the first voltage V1.

Abstract: An apparatus for tracking a peak level of an input signal includes a comparator for comparing the peak level of the input signal with a reference peak voltage signal. A sample and block circuit is coupled to the output of the comparator and is capable of sampling a portion of the input signal. The sampled portion of the input signal is defined by a smart window (timing window) which is received by the sample and block circuit. The sample and block circuit controls a charge pump that determines the level of the reference peak voltage signal. A method of generating a reference peak voltage signal includes receiving an input data, generating a timing window based upon the input data to define a sampling portion in the input data, comparing a level of the reference peak voltage signal with a level of the sampling portion in the input data, and determining a level of the reference peak voltage signal based upon the comparing step.

Abstract: An apparatus of compensating for offset in a received signal generated from a forward path stage, includes a first peak detector for receiving a first signal from the forward path stage and capable of detecting a peak of the first signal; a second peak detector for receiving a second signal from the forward path stage and capable of detecting a peak of the second signal; a differential amplifier coupled to the first peak detector and the second peak detector and capable of generating an offset control signal; and a compensation stage coupled to the differential amplifier and capable of compensating for offset in the received signal in response to the offset control signal.

Abstract: A delay locked loop includes a delay circuit capable of generating an output clock and further capable of generating a GATE signal in response to an aliased condition. A phase detector is coupled to the delay circuit and is capable of comparing a phase difference between a reference clock and the output clock from the delay circuit and generating a pump up signal if the output clock is lagging the reference clock. The phase detector is capable of generating a pump down signal if the output clock is leading the reference clock. A charge pump is coupled to the phase detector and is capable of generating a control voltage for controlling the delay provided to the output clock and capable of pulling up the control voltage in response to the GATE signal.

Abstract: An output driver is provided with driving and filtering capability. An output current driver and output voltage driver embodiments are provided. The output current driver includes, an operational amplifier having a first input for receiving a first input voltage V.sub.1, a second input for receiving a second input voltage V.sub.2, and an output for generating an output voltage Vc. The output current driver also includes a transistor having an input terminal coupled to the output of the operational amplifier for receiving the output voltage Vc, a first terminal coupled to a differential pair, and a second terminal coupled to the second input of the operational amplifier, wherein an output current I.sub.out flows across the transistor. A control current I.sub.CONTROL determines a value of the first input voltage V.sub.1, while the output voltage Vc controls the transistor so that the second voltage V.sub.2 becomes equal to the first voltage V.sub.1.