Abstract: An adjustment circuit for use with a resistive reference ladder that establishes nominal reference steps and a common mode voltage for a plurality of comparators, such as used in a flash converter. An “H” arrangement of current sources injects current at a first node, VH, and sinks at a second node, VL, with VH, and VL, being coupled to ends of the ladder. The voltage difference between these two nodes thus controls the scale applied to the reference ladder, without affecting a common mode voltage reference Vcm. Alternatively, the current source may inject current at VL and sink current at VH to decrease the reference for each comparator.

Abstract: An integrated circuit memory cell and voltage ladder design that adapts techniques typically applied to Static Random Access Memory (SRAM) circuits to implement a compact array of analog Voltage Random Access Memory (VRAM) locations. The memory cells in the VRAM each store a digital value that controls a corresponding switch. The switch couple a particular voltage from a set of voltages generated by the ladder, to be output when that location is enabled. Multiple analog output voltages are provided by simply providing additional rows of cells.

Abstract: An interdigitated Metal-Insulator-Metal (MIM) capacitor provides self-shielding and accurate capacitance ratios with small capacitance values. The MIM capacitor includes two terminals that extend to a plurality of interdigitated fingers separated by an insulator. Metal plates occupy layers above and below the fingers and connect to fingers of one terminal. As a result, the MIM capacitor provides self-shielding to one terminal. Additional shielding may be employed by a series of additional shielding layers that are isolated from the capacitor. The self-shielding and additional shielding may also be implemented at an array of MIM capacitors.

Abstract: A single-ended charge-domain pipeline of at least two stages is provided. Each stage comprises a charge-storage node, a charge-transfer circuit for conveying charge from said charge-storage node out of said stage, a charge-control capacitor connected to said charge-storage node and driven by a periodic clock voltage, a comparator which compares the voltage of said charge-storage node to a reference voltage, and a digital latch which latches the state of said comparator output under control of a second periodic clock voltage and provides a latched digital output from said stage. The second stage of the pipeline further includes a first charge-redistribution capacitor connected to the charge-storage node of the second stage and driven by a conditional voltage responsive to the latched digital output from the first stage. The charge output from each stage of said pipeline is substantially identical to the charge input to said stage.

Abstract: In a differential bucket-brigade device (BBD) pipeline it is necessary for proper circuit function to maintain the common-mode charge within an acceptable range at each pipeline stage. Embodiments of the present invention provide for reducing common-mode charge variations in a differential charge-domain pipeline. Common mode charge at a given stage of the pipeline is adjusted according to one or more measured characteristics, thereby controlling common mode charge variation throughout the differential charge-domain pipeline.

Abstract: An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node ‘Vcmi’. An alternative, switched-capacitor-based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.

Abstract: A technique for correcting errors in Bucket Brigade Device (BBD)-based pipelined devices, such as Analog-to Digital Converters (ADCs). The gain between pipeline stages is desired to be a specific amount, such as unity: that is, all net charge present in each stage ideally is transferred to the next stage. In practical BBD-based circuits, however, the charge-transfer gain is less than ideal, resulting in errors. The approach described herein provides analog correction of such errors due to both capacitor mismatch and to sub-unity charge-transfer gain. In certain embodiments the adjustment circuit may use an adjustable current source and Field Effect Transistor to introduce the correction. In still other embodiments, the adjustment circuit may determine a voltage-feedback coefficient.

Abstract: A technique for dynamically calibrating a successive approximation charge to digital converter by toggling at least some portion of the converter between two predetermined states, with the design goal of balancing the voltage and/or charge that is output in the two states. The two states are chosen such that they are expected to generate the same output voltage when the converter is in “normal” operation mode, e.g., within a fraction of the Least Significant Bit (LSB) resolution of the converter. If there is an imbalance, switching between the two calibration states invariably generates a square wave signal that toggles between two distinct values. A synchronous demodulator having a bandwidth centered at the toggle frequency can then be used to accurately detect an amount of error, which is then feedback to generate correction signals.

Abstract: A charge splitter for separating an incoming charge packet into two outgoing packets while the charge is in a static state, i.e., not while it is flowing down a channel or over a barrier. A splitting gate may have a biasing charge impressed upon it, such as via the application of voltage or current sources to opposite ends thereof, applying a bias to a semiconductor body portion of the gate structure, or by physically separate the splitting gate into multiple sections that each have different applied voltages or currents When discharge barrier gates are operated, different amounts of charge will thus flow to different output storage gates.

Abstract: An integrated circuit memory cell and voltage ladder design that adapts techniques typically applied to Static Random Access Memory (SRAM) circuits to implement a compact array of analog Voltage Random Access Memory (VRAM) locations. The memory cells in the VRAM each store a digital value that controls a corresponding switch. The switch couple a particular voltage from a set of voltages generated by the ladder, to be output when that location is enabled. Multiple analog output voltages are provided by simply providing additional rows of cells.

Abstract: A technique for correcting charge transfer inefficiencies in a Charge Coupled Device (CCD). The basic approach is to estimate the charge entering at a given stage in a CCD pipeline, and to then determine an estimate of the error introduced by the accumulated leftover charge that will be present at a second point, farther down the pipeline. The error is then corrected by injecting a correcting charge at a third point, farther still down the CCD pipeline. The invention is used, in one embodiment, to correct the output of a charge to digital converter, although principals of the invention may be used for other types of circuits.

Abstract: A technique for forming Charge-Coupled Devices (CCDs) in a conventional Complementary Metal Oxide Semiconductor (CMOS) process. A number of single-layer polysilicon gates are formed on an as-grown, native doped silicon substrate, with gaps between them. Masking is used to selectively dope the gates while preventing doping of the silicon in the gaps. Masking may likewise be used to selectively silicide the gates while preventing silicide formation in the gaps. Conventional source-drain processing produces input/output diffusions for the CCD.

Abstract: A Direct Current (DC) charge comparator that provides low input offset by feeding complimentary plus and minus charge inputs to a single amplification path via an alternate input path switch. Multiple sample and hold circuits at the output of the amplification path permit comparison of the result when each of the charge inputs travels down each of the paths, to determine a correction.

Abstract: A charge splitter for separating an incoming charge packet into two outgoing packets while the charge is in a static state, i.e., not while it is flowing down a channel or over a barrier. A splitting gate may have a biasing charge impressed upon it, such as via the application of voltage or current sources to opposite ends thereof, applying a bias to a semiconductor body portion of the gate structure, or by physically separate the splitting gate into multiple sections that each have different applied voltages or currents When discharge barrier gates are operated, different amounts of charge will thus flow to different output storage gates.

Abstract: A technique for forming Charge-Coupled Devices (CCDs) in a conventional Complementary Metal Oxide Semiconductor (CMOS) process. A number of single-layer polysilicon gates are formed on an as-grown, native doped silicon substrate, with gaps between them. Masking is used to selectively dope the gates while preventing doping of the silicon in the gaps. Masking may likewise be used to selectively silicide the gates while preventing silicide formation in the gaps. Conventional source-drain processing produces input/output diffusions for the CCD.

Abstract: A biasing circuit for use with a Charged Coupled Device (CCD) that creates a gate bias voltage by maintaining a model or surrogate representation of the surface potentials within the CCD storage and barrier regions. In one embodiment the invention is a bias circuit that includes at least a first and second model transistor for modeling the two regions. The first model transistor is connected to a supply voltage to provide a first reference voltage at a first node, and models the first charge storage region. A resistive circuit element is coupled between the first node N1 and a second node N2 in order to allow a step voltage to be developed. The second model transistor is in turn connected to the second node N2 and provides the bias voltage at an output portion that can be used to control the gate of the barrier region. The model circuit therefore allows a proper bias voltage to be maintained through process and operating condition variations.

Abstract: A technique for dynamically calibrating a successive approximation charge to digital converter by toggling at least some portion of the converter between two predetermined states, with the design goal of balancing the voltage and/or charge that is output in the two states. The two states are chosen such that they are expected to generate the same output voltage when the converter is in normal operation mode. If there is an imbalance, switching between the two calibration states invariably generates a square wave signal that toggles between two distinct values. A synchronous demodulator having a bandwidth centered at the toggle frequency can then be used to accurately detect an amount of error, which is then feedback to generate correction signals. The detected value of the error signal can in turn can be further integrated over time, to provide a correction value.

Abstract: An integrated circuit memory cell and voltage ladder design that adapts techniques typically applied to Static Random Access Memory (SRAM) circuits to implement a compact array of analog Voltage Random Access Memory (VRAM) locations. The memory cells in the VRAM each store a digital value that controls a corresponding switch. The switch couple a particular voltage from a set of voltages generated by the ladder, to be output when that location is enabled. Multiple analog output voltages are provided by simply providing additional rows of cells.

Abstract: A circuit for adding or subtracting an amount of charge from a charge sample, such as in a Charge Coupled Device (CCD), by portioning and pipelining the processing stages, to avoid introducing a memory effect. The operation, such as subtraction, is split into multiple stages, with each stage responsible for removing only a portion of the total amount of charge that is desired to be removed. The subtraction pipeline stages operate together to remove the total desired charge amount. In one embodiment each successive subtraction stage removes a corresponding lesser amount of charge. As a result, greater accuracy in the amount of charge removed is achieved as well operation at higher frequencies than previous charge subtraction approaches.

Abstract: A Direct Current (DC) charge comparator that provides low input offset by feeding complimentary plus and minus charge inputs to a single amplification path via an alternate input path switch. Multiple sample and hold circuits at the output of the amplification path permit comparison of the result when each of the charge inputs travels down each of the paths, to determine a correction.