Abstract: Methods and apparatus for transporting a synchronous or plesiochronous signal over a packet network. The methods of the invention include providing incoming and outgoing packet counters at the “local” user-network-interface (UNI) where the packets are to be reassembled into a synchronous or plesiochronous signal. According to the basic method of the invention, the UNI is provided with an adjustable clock and the clock rate is adjusted by comparing the incoming packet count with the outgoing packet count. In particular, if the outgoing packet count is smaller than the incoming packet count, the clock rate is increased. If the outgoing packet count is larger than the incoming packet count, the clock rate is decreased. In order to minimize delay in clock adjustments, a “gear shift” adjustment algorithm is provided. The apparatus of the invention includes a phase locked loop (PLL) embodied in a programmable logic device (PLD).

Abstract: Methods of the invention include determining packet size by comparing the RTP timestamps of two consecutive packets, determining the expected (no jitter) local arrival time for the next packet by comparing the difference between the local clock and the timestamp of the present packet and summing it with the timestamp difference of the last two packets, and determining network jitter by comparing the expected local arrival time with the actual local arrival time. Computed network jitter are averaged to determine the average network jitter. The average network jitter is used to set the size of the dynamic buffer. An apparatus for performing the methods is also disclosed.