Abstract: Dynamic data clock rate for data transfer to a display. The rate at which data is transferred from memory by a processor to a display is controlled such that data is transferred at or near one or more pixel refresh rates specified for the display while allowing at least one of the processor or memory to perform other tasks. A rate at which data is transferred from the processor to the display is reduced when the processor and/or memory is burdened with other tasks. When the processor and/or memory become more available as a result of reduction or elimination of other tasks, the rate at which data is transferred from the processor to the display is increased.