Abstract: A system of underwater swarm of robotic fish for monitoring and telepresence. The system comprising a floating platform communicatively coupled to a controller, a submersible sinker communicatively coupled to the floating platform, and a plurality of underwater drones communicatively coupled to the submersible sinker. The controller is configured to receive instructions from an operator for remotely exploring an underwater environment using the submersible sinker and the plurality of underwater drones, transmit the instructions to the plurality of underwater drones via the floating platform and the submersible sinker, the instructions directing the plurality of underwater drones to navigate the underwater environment and collect data, receive the collected data from the plurality of underwater drones via the floating platform and the submersible sinker, and display the collected data to the operator via a virtual display.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.

Abstract: The embodiments herein relates to a hybrid non-volatile memory cell system and architecture for designing integrated circuits. The system comprises CMOS access transistor connected to a memristor which stores a data based on a resistance. The system has a word line for accessing the hybrid memory and two bit lines carrying data of mutually opposite values for transferring a data from the memory. The two terminals of the transistor are connected respectively to a first terminal of the memristor and to a first bit line. The gate terminals of the transistors are coupled together to form a word line. The access transistors control the two bit lines during a read and write operation. A control logic performs a read and write operation with the hybrid memory cells. The memory architecture prevents a power leakage during data storage and controls a drift in a state during a read process.