Abstract: This invention relates to methods and systems for limiting consumption, particularly power consumption, more particularly by appliances in a building, and is generally suitable for integration with building management systems. Embodiments of the invention provide arrangements in which the aggregated power load of a plurality of appliances is capped to a selected value (which may be arbitrary, or may be dictated by conditions) whilst seeking to minimize the deviation from target environmental conditions within the building through a combination of distributed decision making by the appliances themselves and centralized orchestration, which may be informed by real-time sensor readings and/or known properties of the building. The distributed decision-making by individual devices may be based on projected deviation from the target conditions after a period of activity or inactivity but with a central controller which determines which devices should be switched on.

Abstract: This invention relates to methods and systems for controlling consumption, particularly power consumption, more particularly by appliances in a building, and is generally suitable for integration with building management systems. Embodiments of the invention provide methods and systems which probabilistically limit the aggregated power load of a plurality of climate control appliances in a building to a selected value, whilst seeking to minimize the deviation from target environmental conditions within the building. The embodiments of the invention propose distributed decision-making by individual devices based on projected deviation from the target conditions after a period of activity or inactivity.

Abstract: The invention relates to a method and system which provides access control and access control enforcement particularly in relation to business process data streams. Embodiments of the invention provide a method and a set of components (referred to as: Policy Administration Point, Policy Enforcement Point, Filter Updater, Log De-Multiplexer) for fast online filtering of process logs based on access rights. In one embodiment the method comprises a series of steps to (i) encode each user's access rights to the process log in a machine readable format (ii) use such encoding together with incoming process events to compute a custom online filter to be applied to the process log as it is being recorded (iii) execute logical log de-multiplexing, enabling each user to query, inspect and monitor a separate event flow.

Abstract: This invention relates to packet selection techniques that can be used in conjunction with a clock recovery mechanism to mitigate the effects of packet delay variation on timing messages exchanged over a packet network, particularly when seeking to synchronize the time of a clock in a slave device to that of a master clock. The packet selection techniques can assist in reducing the noise in the recovered clock signal at the slave device, allowing recovery to a higher quality. Embodiments of the invention provide techniques based on extracting timing packets that create a constant interval between the arrival of selected packets at the slave device and on extracting timing packets which are closest to making the interval between arrival of the selected packets equal to the interval between the departure of the packets.

Abstract: This invention relates to methods and devices for synchronization using linear programming, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a two-dimensional linear programming technique for estimating clock offset and skew, particularly from two-way exchange of timing messages between a master and a slave device. Some embodiments include a skew and offset adjustable free-running counter for regenerating the master time and frequency at the slave device.

Abstract: This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided.

Abstract: This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a recursive least squares mechanism for clock offset and skew estimation. A major potential advantage of such estimation is that it does not require knowledge of the statistics of the measurement noise and process noise. An implementation using a digital phase locked loop based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client) is also provided.

Abstract: This invention relates to methods and devices for compensating for path asymmetry, particularly with reference to time and frequency synchronization. The invention has particular application where time and frequency synchronization over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP) is being carried out. Typically communication path delays between a time server (master) and a client (slave) are estimated using the assumption that the forward delay on the path is the same as the reverse delay. As a result, differences between these delays (delay asymmetries) can cause errors in the estimation of the offset of the slave clock from that of the master. Embodiments of the invention provide techniques and devices for compensating for path delay asymmetries that arise when timing protocol messages experience dissimilar queuing delays in the forward and reverse paths.

Abstract: This invention relates to methods and devices for time and frequency synchronization. The invention has particular application where time and frequency synchronization over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP) is being carried out. The primary challenge in clock distribution over packet networks is the variable transit delays experienced by timing packets, packet delay variations (PDVs). Embodiments of the invention provide a method for time offset alignment with PDV compensation where a synchronized frequency signal is available at a slave device via Synchronous Ethernet and is used to determine the compensation parameters for the PDV.

Abstract: This invention relates to methods and devices for frequency distribution based on, for example, the IEEE 1588 Precision Time Protocol (PTP). Packet delay variation (PDV) is a direct contributor to the noise in the recovered clock and various techniques have been proposed to mitigate its effects. Embodiments of the invention provide a mechanism to directly measure and remove PDV effects in the clock recovery mechanism at a slave clock. One particular embodiment provides a clock recovery mechanism including a phase-locked loop (PLL) with a PDV compensation feature built-in. An aim of the invention is to enable a slave clock to recover the master clock to a higher quality as if the communication path between master and slave is free of PDV. This technique may allow a packet network to provide clock synchronization services to the same level as time division multiplexing (TDM) networks and Global Positioning System (GPS).

Abstract: This invention relates to methods and devices for clock offset and skew estimation. The invention has particular application in the alignment of slave clocks to a master clock. In embodiments of the invention, the slave clock employs an independent free running clock and a recursive estimation technique to estimate the clock offset and clock skew between the slave and master clocks. The slave can then use the offset and skew to correct the free running clock to reflect an accurate image of the master clock.

Abstract: The embodiments herein relates to a hybrid non-volatile memory cell system and architecture for designing integrated circuits. The system comprises CMOS access transistor connected to a memristor which stores a data based on a resistance. The system has a word line for accessing the hybrid memory and two bit lines carrying data of mutually opposite values for transferring a data from the memory. The two terminals of the transistor are connected respectively to a first terminal of the memristor and to a first bit line. The gate terminals of the transistors are coupled together to form a word line. The access transistors control the two bit lines during a read and write operation. A control logic performs a read and write operation with the hybrid memory cells. The memory architecture prevents a power leakage during data storage and controls a drift in a state during a read process.

Abstract: Systems and methods of synchronizing the frequency of a slave clock to that of a master clock using time-stamps in transmissions from a master device having the master clock, determining an error signal, and adjusting the frequency of the slave clock based on said error signal.

Abstract: This invention relates to methods and devices for entropy-based location fingerprinting, in particular for use over wireless local-area networks (WLANs). The invention has particular application in localization for indoor environments. In embodiments of the invention, an entropy-based fingerprint is determined at a number of predetermined locations within the desired area of localization during an off-line phase and subsequently used in an on-line mode to determine the location of a receiver. In particular embodiments, the fingerprint is a vector of entropy estimates of the channel transfer function (CTF) between a mobile terminal and all access points within coverage. The invention seeks to provide a fingerprinting localization solution that has a simplicity of structure, leading to advantages in storage and pattern recognition requirements, and robustness by proving a unique measure of information that is related to the channel experienced at the location of the mobile terminal.

Abstract: This invention relates to methods and devices for clock synchronization. The invention makes particular use of IEEE 1588 with offset and skew correction. In embodiments of the invention, the IEEE 1588 Precision Time Protocol is used to exchange time stamps between a time server and a client from which the client can estimate the clock offset and skew. In embodiments of the invention a free running clock at the client is provided with an estimation technique based on the time stamps from the IEEE 1588 PTP message exchange between the server and client clocks. The offset and skew from the estimation process can be combined with the local free running clock to give a synchronized local clock which is an accurate image of the master clock.

Abstract: The embodiment herein generally relates to a system to apply moments to a user, particularly during gait. The system is a portable gyroscopic-assisted system, mounted on a user's body, particularly the upper body, particularly to influence orientation of users having difficulty with balancing during gait. The system comprises a plurality of variable-speed control moment gyroscopes (VSCMGs). The VSCMGs generate moments, particularly to counteract a fall to any direction. The VSCMGs are placed close to the center of mass of the user. The couple moments of the VSCMGs are transmitted to the user through a support structure that is tightly attached to the user. Particularly, the system controls moments based on detecting pre-fall conditions.

Abstract: The various embodiments herein provide a Uniform Circular Displaced Sensor Array (UC-DSA) system and method for measuring/estimating Direction of Arrival (DOA) of a wireless signal. The UC-DSA system comprises at least a set of two circular antenna arrays. The two circular antenna arrays have a number of elements. A Radio frequency (RF) receiver captures a wireless signal incident on a circular antenna array. A Direction of Arrival (DOA) estimator processes a received input signal and a Triangulation system provides the exact location of the source of the wireless signal. The two circular antenna arrays with the same number of elements are placed on different radii, and are shifted to have equal separation between inner elements and outer elements.

Abstract: The embodiments herein relates to a hybrid non-volatile memory cell system and architecture for designing integrated circuits. The system comprises CMOS access transistor connected to a memristor which stores a data based on a resistance. The system has a word line for accessing the hybrid memory and two bit lines carrying data of mutually opposite values for transferring a data from the memory. The two terminals of the transistor are connected respectively to a first terminal of the memristor and to a first bit line. The gate terminals of the transistors are coupled together to form a word line. The access transistors control the two bit lines during a read and write operation. A control logic performs a read and write operation with the hybrid memory cells. The memory architecture prevents a power leakage during data storage and controls a drift in a state during a read process.

Abstract: A method and system of scheduling demands on a system having a plurality of resources are provided. The method includes the steps of, on receipt of a new demand for resources: determining the total resources required to complete said demand and a deadline for the completion of that demand; determining a plurality of alternative resource allocations which will allow completion of the demand before the deadline; for each of said alternative resource allocations, determining whether, based on allocations of resources to existing demands, said alternative resource allocation will result in a utilization of resources which is closer to an optimum utilization of said resources; and selecting, based on said determination, one of said alternative resource allocations to complete said demand so as to optimise utilization of resources of the system.

Abstract: This invention relates to methods and devices for motor speed control. The invention has particular application in the control of motors over packet networks. In embodiments of the invention, phase-locked loop principles are used to remotely control the speed of an electric motor over a packet network. The setpoint for the motor is supplied by arriving timestamps from a speed-mapped variable frequency source. The shaft speed of the motor is measured with a tachometer with its output proportional to the motor speed. Any deviation of the actual speed from the setpoint is amplified by the power amplifier whose output drives the motor. Speed control over packet networks allow smoother operation of a process, acceleration control, different operating speeds for each process recipe, compensation for changing process variables, slow operation for setup purposes, adjustments to the rate of production, accurate positioning, and control torque or tension of a system.