Abstract: A memory capacity test method capable of confirming the memory capacity of an actually mounted memory in a short time in a memory system which mounts a memory only on a portion of a memory space. The method writes first data to a check address which is an n-th power of two, and then second data to the address 0, where the second data differs from the first data, and decides that the memory is not mounted on the check address if the data read from the check address disagrees with the first data. This is based on the fact that the check address actually points the address 0 when the memory is not mounted on the check address of the nth power of two, and hence the second data is written over the first data on the address 0 in that case.

Abstract: Sampled points are connected by lines to form a line pattern which may have a steady portion and a suddenly changing portion. Various line patterns are classified into several classes depending on rates of change of slopes of the line patterns. When a line pattern transits from the steady portion to the suddenly changing portion, or vice versa, before or after a sampled point, the differential coefficient of an interpolation curve at the sampling point is made closer to the slope in the steady portion. Sampled signals having sudden transitions can thereby be interpolated without undue fluctuations before and after the transitions.

Abstract: An AC power supply apparatus for obtaining sampled data required for the FFT (Fast Fourier Transformation) by an A/D converter. Since a clock pulse train for forming an output voltage (power supply output) is used as sample clock pulses, sampled data associated with exactly one period can be obtained. This eliminates the need for the window processing. This makes it possible to provide a low cost, error-free apparatus.

Abstract: An automatic calibration circuit for a maximum and minimum value detection apparatus including a maximum value detection circuit for detecting and outputting a maximum value of an input signal, and a minimum value detection circuit for detecting and outputting a minimum value of the input signal. In a calibration mode, a reference signal of a fixed value is automatically inputted to the maximum value detection circuit and to the minimum value detection circuit upon entry of a calibration mode. An offset voltage of at least one of the maximum value detection circuit and the minimum value detection circuit is automatically adjusted so that the maximum value and the minimum value obtained in response to the reference signal become equal.

Abstract: A vertical amplifier system for a multitrace oscilloscope including a first and a second variable gain amplifiers each connected to each channel of a multitrace oscilloscope. First, a first reference voltage is fed to the two variable gain amplifiers at the same time. The polarity of output of the second variable gain amplifier is inverted, and the inverted output is added to the output of the first variable gain amplifier by an adder. The added result is detected by a resistor. A CPU automatically controls a gain of at least one of the variable gain amplifiers while receiving the added result so that the added result becomes zero. Second, a second reference voltage (a ground level voltage, for example) is applied to both variable gain amplifiers, and an offset of at least one of the variable gain amplifiers is adjusted so that the added result detected by the resistor becomes zero. The input-output characteristics of both variable gain amplifiers are equalized with high accuracy.

Abstract: A trigger source switching circuit including a first switch system for a high frequency region, and a second switch system for a low frequency region. The first switch system is composed of a plurality of semiconductor switches having good frequency and isolation characteristics, and the adverse effect of the DC shift is eliminated by using a capacitor connected between the outputs of the semiconductor switches and the output terminal of the trigger source switching circuit. The second switch system for the low frequency region is composed of analog switches, and the output terminal of each analog switch is connected to an input terminal of an operational amplifier of a small output offset, thereby reducing the effect of the on-resistance of the analog switches and the adverse effect of the DC shift. The analog switches can be used because the frequency and isolation characteristics required in the high frequency region are unnecessary in the low frequency region.

Abstract: A data display apparatus with a function for correcting the effect of external magnetic field including a display, a driving circuit for driving the display, an adjuster for adjusting a display position of input signal, a detector for detecting an output voltage of the driving circuit, and a difference detection circuit. The difference detection circuit detects a difference between an output of the detector when a predetermined reference signal is inputted as the input signal and an output of the detector when a display position of the predetermined reference signal is adjusted to a reference position on the screen of the display by the adjuster. The difference is stored in a memory as calibration data for correcting the effect of external magnetic field or the like.

Abstract: A glitch detection circuit having an A/D converter, a state holding circuit, a discrimination circuit and a storing circuit. The A/D converter samples an input signal at a predetermined sampling interval to produce digital data during a predetermined acquisition interval which is longer or equal to the sampling interval. The state holding circuit is connected to an output terminal of the A/D converter, and holds a distribution state of the digital data in the predetermined acquisition interval. The discrimination circuit detects a maximum value and a minimum value during the acquisition interval based on the digital data held in the state holding circuit, and the storing circuit stores the maximum value and the minimum value produced from the discrimination circuit for each acquisition interval.

Abstract: A band limiter connected between output lines of a differential amplifier. The band limiter includes a bipolar transistor connected to the output lines via capacitors, and includes a temperature detecting device for detecting ambient temperature. Transistor capacitance is connected to or disconnected from the output lines in response to a bandwidth limiting signal. The transistor constitutes a low-pass filter functioning as a band limiter when it is closed, whereas it functions as a variable capacitor which varies its capacitance in accordance with the ambient temperature when it is opened. The high-band frequency characteristic of the differential amplifier is temperature compensated by the transistor functioning as a variable capacitance.

Abstract: A negative feedback amplifier including, in an input stage, a common-emitter first transistor and a common-base second transistor for supplying a quiescent collector current (standing current) to the first transistor so that a sufficient standing current flows. A negative feedback circuit is connected between an output terminal of an output stage and the emitter of the second transistor, and a first limiter diode is parallely connected to the feedback circuit so as to prevent saturation of an NPN transistor of the output stage. The common-base transistor in the input stage makes it possible to select a high resistance resistor as a feedback resistor, thus enabling the standing current of the output stage to be reduced. A second limiter diode may be connected between the output terminal and the input terminal of the output stage.

Abstract: An FET buffer amplifier having a serially connected input FET and bias current FET. The drain or source current of the input FET is detected by a detection resistor and the detected voltage is negatively fed back to the gate of the bias current FET so that the source current of the input FET is maintained at a fixed value. This can achieve a low output impedance, high input impedance, wideband buffer amplifier with a simple circuit.

Abstract: A vertical amplifier apparatus with a beam-finding function for an oscilloscope including an analog multiplier and a gain control circuit. The analog multiplier multiplies an input signal to the vertical amplifier by a gain control signal. The gain control circuit outputs a DC voltage as the gain control signal. In a beam-finding mode, the gain control circuit supplies the analog multiplier with the gain control signal whose absolute value is much smaller than that of the gain control signal in a normal mode. This makes is possible to obviate a dedicated beam-finder circuit. In a multi-channel oscilloscope, the beam-finding operation can be performed independently for each channel.

Abstract: A linear interpolator comprising an amplifier, an integrator for integrating an output of the amplifier, a feedback circuit connected between the amplifier and the integrator for bootstrapping an input voltage of the amplifier by an output voltage from the integrator, and a switch for periodically supplying a staircase input signal to the amplifier. A linearly interpolated output is derived from the integrator. The discrete input signal changing stepwise can be linearly interpolated with high accuracy.