Abstract: Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.

Abstract: A memory cell based upon thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells. Special circuitry provides lowered power consumption during standby.

Abstract: A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

Abstract: Voltage reference circuits configured to generate a voltage reference with a programmable temperature slope are disclosed. By combining and programming a PTAT (Proportional To Absolute Temperature) voltage generation circuit and a CTAT (Complementary To Absolute Temperature) voltage generation circuit, desired temperature slope for the voltage reference is obtained. To adjust both temperature slope and offset of the voltage reference, the voltage reference circuits include a bandgap reference circuit. The bandgap reference circuit is used to create a temperature independent current, which is coupled to a programmable string of resistors and programmable string of MOSFETs to produce a desired temperature slope for the voltage reference. The desired offset of the voltage reference is obtained by the temperature-independent current into another string of programmable resistors. A circuit architecture and method to control the temperature slope and offset of the voltage reference independently is disclosed.

Abstract: A differential current sensing circuit architecture is used with an integrated circuit NVM memory block in which a selected memory cell and a related complementary memory cell are accessed at the same time for reading. The circuit architecture is used not only for normal operations for reading the logic states of a selected memory cell and its complementary memory cell after programming, but also for reading the logic states of a selected memory cell and its complementary memory cell before programming for the detecting of faults in memory cells.

Abstract: Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract: A one time programmable nonvolatile memory formed from metal-insulator semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting lines formed in a semiconductor substrate. Among others, features include forming the gate lines with polysilicon layers of one conductivity type and the intersecting lines with dopants of the opposite conductivity type in the substrate; forming the intersecting lines with differing dopant concentrations near the substrate surface and deeper in the substrate; and forming the widths of the gate lines and intersecting lines with the minimum feature size that can be patterned by a particular semiconductor technology.

Abstract: A method of programming one-time programmable (OTP) memory cells in an array is described. Each memory cell has a MOSFET programming element and a MOSFET pass transistor, the MOSFET pass transistor having a gate electrode over a channel region between two source/drain regions, and the MOSFET programming element having a gate electrode over a channel region contiguous to a source/drain region either part of, or connected to, one of the two source/drains associated with the MOSFET pass transistor. The other source/drain region of the MOSFET pass transistor is coupled to a bit line. The memory cell is programmed by setting a first voltage of a first polarity on the gate electrode of the pass transistor to electrically connect the source/drain regions of the pass transistor; setting a second voltage of the first polarity on the gate electrode of the programming element; and setting a third voltage of a second polarity on the bit line.

Abstract: Techniques are provided for managing voltages on memory cells in a cross-point array during a read operation. The techniques apply to vertical layer thyristor memory cells and non-thyristor memory cells. Voltages on selected bitlines (e.g., corresponding to memory cells from which data is to be read), are set to a read voltage level. Voltages on unselected bitlines (e.g., corresponding to memory cells from which data is not to be read and which are not to be disturbed) are set to a de-bias voltage level that is different from the read voltage level.

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.

Abstract: Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.

Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

Abstract: For a block of memory cells interconnected by single-ended bit lines, a sense amplifier receives the input from a single-ended bit line to determine the logic state of a selected memory cell connected to the single-ended bit line. The sense amplifier also receives a reference voltage generated from a base-emitter voltage of a emitter follower bipolar transistor. The base-emitter voltage is controllably divided by a voltage divider network with selectable resistive elements to tune the reference voltage.

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract: A six-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. Methods of increasing the operational speed in reading the contents of a selected memory cell in an array of such memory cells while lowering power consumption, and of avoiding an indeterminate memory cell state when a memory cell is “awakened” from Standby are described.

Abstract: Bandgap Voltage Reference circuits configured to produce reference voltages with both voltage offset and a voltage temperature slope are disclosed. By generating the voltage offset from a temperature-independent current, the voltage offset of the reference voltage may be temperature-independent, while generating the voltage temperature slope from a temperature-dependent current allows the voltage temperature slope to vary with temperature. To ensure that the voltage offset remains independent from the voltage temperature slope, an apparatus is disclosed for orthogonal trimming of voltage offset and voltage temperature slope.

Abstract: The access speeds of new memory technologies may not be compatible with product specifications of existing memory technologies such as DRAM, SRAM, and FLASH technologies. Their electrical parameters and behaviors are different such that they cannot meet existing memory core specifications without new architectures and designs to overcome their limitations. New memories such as STT-MRAM, Resistive-RAM, Phase-Change RAM, and a new class of memory called Vertical Layer Thyristor (VLT) RAM requires new read sensing and write circuits incorporating new voltage or current levels and timing controls to make these memory technologies work in today's systems. Systems and methods are provided for rendering the memory cores of these technologies transparent to existing peripheral logic so that they can be easily integrated.

Abstract: Techniques are provided for managing voltages applied to memory cells in a cross-point array during a write operation (e.g., to transition from a resistive state into a conductive state). The techniques apply to thyristor memory cells and non-thyristor memory cells. Bitlines, connected by a wordline, are preconditioned to a voltage level, by a precondition device, to write data to one or more memory cells at intersections of the bitlines and the wordline. Each bitline is coupled to a high impedance device, a detect device, a precondition device and a clamp device. When a memory cell on a first bitline transitions from a resistive state into a conductive state, it pulls a voltage level of the first-bit line level low. A first clamp device maintains the voltage level at a level to de-bias the first bitline from the wordline, while other memory cells to be written along the wordline remain biased.

Abstract: A circuit arrangement and method of reading the logic state of a memory cell in an array of semiconductor memory cells. A data memory cell selected from the array drives a current on a first data bit line in a read operation. A reference memory cell corresponding to the memory cell is activated after the memory cell is selected, the reference memory cell driving a current through the reference data line at a greater rate than that of the corresponding memory cell regardless of the logic state of the memory cell. A sense amplifier connected to the data line and a reference data line determines the logic state of the selected memory cell. A delay circuit activates the reference memory cell after the memory cell is selected and enables the sense amplifier after the reference memory cell has been activated.