Abstract: A two-phase boost converter is provided. The converter includes a first boost converter coupled between an input node and a common node; and a second boost converter coupled between the input node and an output node, wherein the second boost converter comprises: a first transistor coupled between ground and an internal node, an inductor coupled between the input node and the internal node, a capacitor coupled between the internal node and the common node, and a second transistor coupled between the common node and the output node.

Abstract: Adaptive on-time switching voltage regulator circuits and methods therefor provided. In some embodiments, a voltage regulator comprises: a switching circuit configured to generate a switching signal at a switching node according to a pulse-width modulated (PWM) signal; a phase-lock loop (PLL) configured to lock the PWM signal to a clock reference signal, the PLL comprising: a PWM signal generator configured to generate the PWM signal according to an error signal, and a phase detector configured to generate the error signal based on the PWM signal and the clock reference signal.

Abstract: A system that provides intelligent constant on-time control may include a first switch coupled to a power input; a second switch coupled to the first switch; a switching node between the first switch and the second switch, the switching node configured to be connected to an inductor and a power output; feedback paths coupled to (1) a synthesized node and (2) the power output, the feedback paths enabling feedback of signals from (1) the synthesized node, and (2) the power output; and a controller coupled to the feedback paths. The controller may be configured to control a voltage at the power output based on a combination of the signals carried by the feedback paths.

Abstract: Voltage regulator circuits and methods therefor provided. In some embodiments, a voltage regulator circuit comprises: a first switch coupled to a power input; a second switch coupled to the first switch; a switching node between the first switch and the second switch; an inductor coupled between the switching node and an output node; a capacitor coupled between the output node and ground; a driver configured to operate the first and second switches according to a pulse-width-modulated (PWM) signal; a PWM circuit configured to generate the PWM signal based on at least an error signal; and a phase detector configured to generate the error signal based on a phase difference between the PWM signal and a clock reference signal.

Abstract: A data transmission method and system for enhanced channel coding efficiency of a DisplayPort interface is disclosed. One method comprises transmitting a plurality of coding units for each micro-packet in each of one or more lanes of a DisplayPort Main Link from a DisplayPort transmitter, wherein each of the coding units comprises: a group of m symbol chunks, each symbol chunk including four 8-bit symbols, wherein m is 2 or 4; and an n-bit code data indicator that precedes the group of m-symbol chunks, wherein n is 2 or 4, and wherein the n-bit code data indicator indicates a content type of the m symbol chunks.

Abstract: A power switch may be coupled to a power input, a first capacitor, a second capacitor, and a power output. A first switch may be coupled to the first capacitor. A second switch may be coupled to the second capacitor. A current sensor may be configured to measure a first current of the first capacitor and a second current of the second capacitor. A controller may be configured to determine whether the first capacitor and the second capacitor shorts or opens based on the first current and the second current, respectively. The controller may generate one or more alerts based on opening/shorting of a capacitor, and may open a switch based on shorting of a capacitor.

Abstract: A system for managing power on distributed devices may include a first device having a master logic and a second device having a slave logic. The master logic may enable the first device to communicate with multiple devices having the slave logic on one or more channels. The slave logic may enable the second device having the slave logic to communicate with the first device and to communicate with a third device having the slave logic. The slave logic may enable the multiple devices having the slave logic to manage operations of the distributed devices.

Abstract: A system that uses pulse-based communication may include a first device and a plurality of devices on a series connection. The first device may have a master circuit and the plurality devices may have a slave circuit. The master circuit may enable the first device to communicate with the plurality devices having the slave circuit on the series connection. The master circuit may enable the first device to send a pulse string including one or more pulses to the plurality devices. The slave circuit may enable the plurality devices to receive the pulse string from a previous device on the series connection and change the pulse string. The slave circuit may enable the plurality devices to send the pulse string to a next device on the series connection. Each of the plurality devices may determine its address in the series connection based on the pulse string it receives.

Abstract: A system that provides intelligent constant on-time control may include a first switch coupled to a power input; a second switch coupled to the first switch; a switching node between the first switch and the second switch, the switching node configured to be connected to an inductor and a power output; feedback paths coupled to (1) the switching node and (2) the power output, the feedback paths enabling feedback of signals from (1) the switching node, and (2) the power output; and a processor coupled to the feedback paths. The processor may be configured to control a voltage at the power output based on a combination of the signals carried by the feedback paths.

Abstract: A data transmission system includes a transmitter having a first switching re-timer and a receiver having a second switching re-timer. The first switching re-timer is configured to double a link rate per lane and halve the number of lanes, and the second switching re-timer is configured to halve the doubled link rate and double the halved number of lanes.

Abstract: A switching regulator may comprise an inductor housed in an inductor housing, a wire electrically coupled to the inductor and housed in the inductor housing, an electrical component including a terminal, and a board including a board trace. The board trace may electrically couple the terminal with first wire. The electrical component and the inductor housing may be attached to the board. The attachment of the inductor housing to the board may create a space between the inductor housing and the board. The electrical component may be disposed within the space.

Abstract: A system for managing power on distributed devices may include a first device having a master logic and a second device having a slave logic. The master logic may enable the first device to communicate with multiple devices having the slave logic on one or more channels. The slave logic may enable the second device having the slave logic to communicate with the first device and to communicate with a third device having the slave logic. The slave logic may enable the multiple devices having the slave logic to manage operations of the distributed devices.

Abstract: A switching regulator may include an inductor housing, a board, and one or more electrical components. The inductor housing may house an inductor and one or more wires. The board may include one or more board traces and one or more solder pads. The electrical components may include one or more chips, capacitors, voltage sources, and/or other electrical components. The inductor housing may be attached to the board to create a space between the inductor housing and the board. The space may be created underneath the inductor housing and above the board. One or more electrical components may be attached to the board. One or more electrical components may be disposed within the space.

Abstract: A slotted gate power transistor is a lateral power device including a substrate, a gate dielectric formed over the substrate, a channel region in the substrate below the gate dielectric and gate electrode layer formed over the gate dielectric. The gate electrode layer overlaps the gate dielectric above the channel region, an accumulation region, and a drift region below an oxide filled shallow trench isolation (or STI) or locally oxidized silicon (LOCOS) region. The slotted gate power transistor includes one or more slots or openings on the gate electrode layer over the accumulation region. Electrical connectivity is maintained over the entire gate electrode layer without external wiring.

Abstract: A slotted gate power transistor is a lateral power device including a substrate, a gate dielectric formed over the substrate, a channel region in the substrate below the gate dielectric and gate electrode layer formed over the gate dielectric. The gate electrode layer overlaps the gate dielectric above the channel region, an accumulation region, and a drift region below an oxide filled shallow trench isolation (or STI) or locally oxidized silicon (LOCOS) region. The slotted gate power transistor includes one or more slots or openings on the gate electrode layer over the accumulation region. Electrical connectivity is maintained over the entire gate electrode layer without external wiring.

Abstract: A slotted gate power transistor is a lateral power device including a substrate, a gate dielectric formed over the substrate, a channel region in the substrate below the gate dielectric and gate electrode layer formed over the gate dielectric. The gate electrode layer overlaps the gate dielectric above the channel region, an accumulation region, and a drift region below an oxide filled shallow trench isolation (or STI) or locally oxidized silicon (LOCOS) region. The slotted gate power transistor includes one or more slots or openings on the gate electrode layer over the accumulation region. Electrical connectivity is maintained over the entire gate electrode layer without external wiring.

Abstract: The invention teaches a semiconductor circuit for driving an LED in which the current passing through the LED is regulated by adjusting the NMOS Rdson using a series of digital signals. The circuit maintains a high current accuracy over wide range of current changes while keeping a low voltage drop.