Abstract: A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through tis second and third transistors.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.

Abstract: Various implementations relate to receiving, by a non-volatile memory device from a host, a host command include device context information of non-volatile memory devices. The device context includes an address of a buffer of each non-volatile memory device. In response to receiving the host command, portions of host data are divided among the non-volatile memory devices. The non-volatile memory device sends to the host a transfer request indicating transfer of each portion of the host data to a respective one of the non-volatile memory devices. The non-volatile memory device sends to another non-volatile memory device a peer command based on the device context information.

Abstract: Various implementations relate to grouping a plurality of non-volatile memory devices into at least one first group, determining that a number of the at least one first group is greater than 1, selecting a first leader device from first non-volatile memory devices in each of the at least one first group, and determining first result data by performing an operation based on first data from at least one of the first non-volatile memory devices in each of the at least one first group.

Abstract: According to one embodiment, a semiconductor memory device includes a first insulating layer; a first conductive layer provided in the first insulating layer and extending in the first direction; a second conductive layer extending in the first direction and provided adjacent to the first conductive layer in a second direction; and a contact plug coupled to one surface of the first conductive layer in a third direction. Thicknesses in the third direction of portions of the first and second conductive layers that overlap the contact plug in the third direction are smaller than thicknesses in the third direction of portions of the first and second conductive layers that do not overlap the contact plug in the third direction.

Abstract: A semiconductor storage device of an embodiment includes a plurality of conductive layers and a plurality of insulation layers, a first contact plug, and a second contact plug. The plurality of conductive layers and the plurality of insulation layers are alternately stacked in a first direction. The first contact plug contacts a first conductive layer included in the plurality of conductive layers and extends in the first direction. The second contact plug contacts a second conductive layer that is a conductive layer directly above the first conductive layer of the plurality of conductive layers and extends in the first direction through the first conductive layer. The second contact plug includes a second conductor layer, and an insulation layer that is provided between the second conductor layer and the first conductive layer and is configured to insulate the second conductor layer and the first conductive layer.

Abstract: An information processing apparatus that updates a regression coefficient parameter based on a predetermined objective function including a regularization term for each of a plurality of elements characterized by a task and a feature value, the information processing apparatus comprising processing circuitry. The processing circuitry selects an element which is an update target of the regression coefficient parameter from the plurality of elements, fixes a value of the regularization term of an unselected element, selects a calculation expression for updating a regression coefficient parameter of the selected element based on a regression coefficient parameter of the unselected element, and updates the regression coefficient parameter of the selected element based on the selected calculation expression.

Abstract: A semiconductor device includes: a wiring substrate; at least one first semiconductor element provided above the wiring substrate; a first resin layer configured to seal the first semiconductor element; and a second resin layer provided on an outer surface of the first resin layer. A Young's modulus of the second resin layer is greater than a Young's modulus of the first resin layer, and/or a linear thermal expansion coefficient of the second resin layer is greater than a linear thermal expansion coefficient of the first resin layer.

Abstract: In one embodiment, a semiconductor device includes a stacked film including a plurality of first insulators and a plurality of electrode layers that are alternately stacked in a first direction. The device includes a first plug provided on a first electrode layer among the plurality of electrode layers, and having a tube shape extending in the first direction. The device includes a second insulator provided in the first plug and the first electrode layer, and having a columnar shape extending in the first direction. Furthermore, a diameter of a side face of the first plug enclosing the second insulator is larger than a diameter of a side face of the first electrode layer enclosing the second insulator.

Abstract: Various implementations relate to receiving, by a first non-volatile memory device from a host, a host command including device context information of a plurality of non-volatile memory devices. The device context includes an address of a buffer of each of the plurality of non-volatile memory devices, in response to receiving the host command. The first non-volatile memory device divides portions of host data corresponding to the host command among the plurality of non-volatile memory devices. The first non-volatile memory device sends to the host a transfer request indicating transfer of each of the portions of the host data to a respective one of the plurality of non-volatile memory devices. The first non-volatile memory device sends to each of the plurality of non-volatile memory devices other than the first non-volatile memory device, a peer command based on the device context information.

Abstract: According to one embodiment, there is provided a method of managing a manufacturing line. The method comprises obtaining a capability variation characteristic of each resource based on a throughput result of a process area among multi process areas arranged in the manufacturing line, each of the process areas including a multi resources. The method comprises determining number of additional resources for achievement of a quota in the process area based on the number of resources in the process area and the obtained capability variation characteristic.

Abstract: A data generation apparatus of one embodiment includes a processing unit, an evaluation unit, and a conversion unit. The processing unit designs, through optical proximity correction based on a target pattern formed on a substrate using the photomask, a mask pattern corresponding to the target pattern and including a plurality of rectangular regions. The evaluation unit evaluates the mask pattern using a cost function having, as a parameter, a jog length indicating a length of each of the rectangular regions included in the mask pattern in a first direction. The conversion unit converts mask pattern data indicating the mask pattern with an evaluation that meets a predetermined condition to drawing data corresponding to a variable shaped beam drawing process.

Abstract: A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.

Abstract: A memory system according to an embodiment includes a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks. The memory controller includes first and second tables, and first and second storage areas. The first table is managed in units of map segments. The second table includes first entries associated with a plurality of map segments included in the first table. The first storage area is configured to store a change history of the first table. The second storage area is configured to store a physical address of a block that is a storage destination of a copy of a changed map segment and a change history of the second table.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip including a first metal pad and a second metal pad; and a second semiconductor chip including a third metal pad and a fourth metal pad, the third metal pad joined to the first metal pad, the fourth metal pad coupled to the second metal pad via a dielectric layer, wherein the second semiconductor chip is coupled to the first semiconductor chip via the first metal pad and the third metal pad.

Abstract: A semiconductor memory device includes a semiconductor substrate, a memory cell array, and first and second wirings. The semiconductor substrate includes first region to third region and fourth region to sixth region. The memory cell array includes first conducting layers extending in a second direction from the first region to the third region and laminated in a first direction, first and second semiconductor layers disposed in the first and third regions, extending in the first direction, and opposed to the first conducting layers, first and second contacts disposed in the fourth and sixth regions and extending in the first direction, and a third semiconductor layer disposed in the fifth region and extending in the first direction. The first wiring is connected to the first semiconductor layer and the second contact. The second wiring is connected to the second semiconductor layer and the third contact.

Abstract: According to one embodiment, a storage device includes a non-volatile memory and a control unit that is electrically connected to the non-volatile memory and that is configured to control the non-volatile memory. The control unit is configured to manage a plurality of management areas obtained by logically partitioning storage area of the non-volatile memory, when a write request is received that includes data for which a valid term has been set, determine, based on the valid term, a first management area from among the management areas, write the data included in the write request to the determined first management area, and when the data written to the first management area is erased, collectively erase all data written in the first management area which includes the data.

Abstract: According to one embodiment, a semiconductor memory device includes a first string unit including a first memory string including a first selection transistor and a first memory cell coupled to the first selection transistor, a second string unit including a second memory string including a second selection transistor and a second memory cell coupled to the second selection transistor, a first select gate line, a second select gate line, a first bit line, a second bit line, and a first word line. Both of the first select gate line and the second select gate line are selected in a first read operation. The first select gate line is selected and the second select gate line is not selected in a second read operation.

Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.

Abstract: A semiconductor memory device includes memory cells, a first circuit that includes a first latch group including first and second data latch circuits and a second latch group including third and fourth data latch circuits, and a control circuit configured to control a write operation during which first and second data to be written into the memory cells are stored in the first and second data latch circuits, respectively, wherein the first and second data are also stored in the third and fourth data latch circuits, respectively, while the first and second data stored in the first and second data latch circuits, respectively, are being written in the memory cells.