Abstract: Methods and systems for reading out a pixel array are provided. An example system may be configured to represent the activity of at least two pixels in the array as at least two digital signals. Further, the example system may be configured to dynamically aggregate the at least two digital signals into one representative analog signal corresponding to the activity of the at least two pixels.

Abstract: A delay circuit is provided. The delay circuit includes a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay circuit. Furthermore, the delay circuit is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge an input signal being actively delayed by the delay circuit when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.

Abstract: Methods and systems for reading out a pixel array are provided. An example system may be configured to represent the activity of at least two pixels in the array as at least two digital signals. Further, the example system may be configured to dynamically aggregate the at least two digital signals into one representative analog signal corresponding to the activity of the at least two pixels.

Abstract: Methods and systems for reading out a pixel array are provided. An example system may include a plurality of pixels. The system may further include an interface circuit configured to provide an analog signal at a sense node. The analog signal may represent the activity of at least two pixels. The interface circuit may include a plurality of capacitors of which at least one capacitor is connected at one end to an output stage of a pixel and at another end to the sense node. The system may further include a readout circuit configured to convert the analog signal at the sense node to a digital signal.

Abstract: Methods and systems for reading out a pixel array are provided. An example system may include a plurality of pixels. The system may further include an interface circuit configured to provide an analog signal at a sense node. The analog signal may represent the activity of at least two pixels. The interface circuit may include a plurality of capacitors of which at least one capacitor is connected at one end to an output stage of a pixel and at another end to the sense node. The system may further include a readout circuit configured to convert the analog signal at the sense node to a digital signal.

Abstract: A delay circuit is provided. The delay circuit includes a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay circuit. Furthermore, the delay circuit is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge an input signal being actively delayed by the delay circuit when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.

Abstract: Methods and systems for reading out a pixel array are provided. An example system may be configured to represent the activity of at least two pixels in the array as at least two digital signals. Further, the example system may be configured to dynamically aggregate the at least two digital signals into one representative analog signal corresponding to the activity of the at least two pixels.

Abstract: A circuit is provided. The circuit includes a single-photon avalanche diode. The circuit further includes a delay element comprising a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay element. The delay element is configured to receive, at an inverting section, an event signal indicative of an avalanche event in the single-photon avalanche diode. Furthermore, the delay element is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge of the event signal being actively delayed by the delay element when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.

Abstract: Methods and systems for reading out a pixel array are provided. An example system may be configured to represent the activity of at least two pixels in the array as at least two digital signals. Further, the example system may be configured to dynamically aggregate the at least two digital signals into one representative analog signal corresponding to the activity of the at least two pixels.