Abstract: The present invention, generally speaking, takes advantage of the foregoing capability to determine and display the X,Y location corresponding to a net name, by translating functional test data of a digital logic chip passed through a simulation model which identifies one or more defective nets of the chip. The defective nets are processed against a database of the foregoing type to obtain X,Y coordinate data for these nets, allowing them to be data logged as physical traces on the chip layout. In accordance with an exemplary embodiment, this mapping is performed by taking the output from a functional tester and translating it from a list of failed scan chains into a list of suspected netlist nodes. The X,Y coordinates of suspected netlist nodes are then identified and stored in a database, providing failure analysis and yield enhancement engineers a starting point for performing failure analysis and for immediately understanding whether “in-line” inspection data can account for a given failure.

Abstract: An intelligent, state-based macro facility is provided (as opposed to the unintelligent keystroke macro facilities typical of the prior art). Instead of a record time and an end time, an intelligent, state-based macro, or "smart macro," has only a single "capture" time, determined by the user pressing a single "smart macro" key. The state of the application, including objects displayed and various properties or attributes of those objects, is then captured and stored under a name supplied by the user. That same state may then be applied to different data to produce the same kinds of results. The smart macro may be applied interactively by the user to different data, or different data sets. Even more advantageously, a batch job may be scheduled, in which the smart macro is scheduled to run on specified data at a specified time with the results being saved to disk under a user-specified name. Batch jobs may be scheduled as one-time jobs or recurring jobs.

Abstract: An integrated circuit of the present invention comprises antifuse elements which have been fabricated by depositing at under 500.degree. C. an antifuse layer approximately 30 nanometers to 400 nanometers between layers of titanium (Ti), said antifuse layer comprising a stoichiometric or off-stoichiometric amorphous silicon-based dielectric layer, such that a heating of the said antifuse layer in excess of 500.degree. C. by electrical or energy beam means will cause a chemical reduction reaction between the titanium and silicon-dioxide layers that yields more Ti.sub.5 Si.sub.3, TiSi, and/or TiSi.sub.2 than is yielded TiO, Ti.sub.2 O.sub.3, Ti.sub.3 O.sub.5, and/or TiO.sub.2, and such that there results a conductive compound between said titanium layers which constitutes a short circuit.

Abstract: A system for testing integrated circuits is disclosed which uses a mechanical microprobe and the integrated circuit's CAD database. The system is integrated with the CAD database in such a manner that after an initial alignment operation between the CAD database and the integrated circuit being tested, the microprobe can be moved automatically to any spot on the circuit by choosing a point in the CAD database and placing a cursor on that spot. The microprobe is then automatically moved to the point so indicated. A contact sensing circuit allows the probe to be driven into the actual circuit to take measurements or inject test signals without fear of damaging the integrated circuit. The system can operate in numerous modes, each of which provide a different way of visualizing the circuit being tested.

Abstract: A technique for detecting whether electrical contact between a probe tip and a device under test ("DUT") has been established. A contact sensing circuit has a ground that is isolated from the ground of the DUT (and remaining portions of the test equipment) during contact sensing. The contact sensing circuit has elements that operate to apply a characteristic signal to one of the DUT terminals, such as its ground terminal. This causes virtually all the DUT circuit traces to track the applied signal (relative to the contact sensing ground). The contact sensing circuit further includes elements, coupled to the probe, that operate to detect the presence of the characteristic signal (relative to the contact sensing ground) on the probe. Once electrical contact has been established, the characteristic signal output is disconnected from the DUT, the test equipment ground is connected to the contact sensing circuit ground, and the probe output is coupled to the relevant portions of the test equipment circuitry.