Abstract: A memristor apparatus includes meta-stable switching elements and an AHAH (Anti-Hebbian and Hebbian) feedback mechanism that operates the meta-stable switching elements by controlling the electric field across the meta-stable switching elements. The meta-stable switching elements form a device with an electrical resistance. Additionally, in some example embodiments the memristor apparatus can include a synapse apparatus comprising a differential pair of memristor apparatuses including the memristor apparatus.

Abstract: Methods and systems for feature extraction of LIDAR surface manifolds. LIDAR point data with respect to one or more LIDAR surface manifolds can be generated. An AHAH-based feature extraction operation can be automatically performed on the point data for compression and processing thereof. The results of the AHAH-based feature extraction operation can be output as a compressed binary label representative of the at least one surface manifold rather than the point data to afford a high-degree of compression for transmission or further processing thereof. Additionally, one or more voxels of a LIDAR point cloud composed of the point data can be scanned in order to recover the compressed binary label, which represents prototypical surface patches with respect to the LIDAR surface manifold(s).

Abstract: An AHaH (Anti-Hebbian and Hebbian) apparatus for use in electronic circuits. Such an AHaH apparatus can include one or more meta-stable switches, and one or more differential pairs of output electrodes, wherein each electrode among each differential pair of output electrodes can include one or more input lines coupled thereto via one or more of the meta-stable switch.

Abstract: An AHaH (Anti-Hebbian and Hebbian) apparatus for use in electronic circuits. Such an AHaH apparatus can include one or more meta-stable switches, and one or more differential pairs of output electrodes, wherein each electrode among each differential pair of output electrodes can include one or more input lines coupled thereto via one or more of the meta-stable switch.

Abstract: Methods and systems for constructing biological-scale hierarchically structured cortical statistical memory systems utilizing fabrication technology and meta-stable switching devices. Learning content-addressable memory and statistical random access memory circuits are detailed. Additionally, local and global signal modulation of bottom-up and top-down processing for the initiation and direction of behavior is disclosed.

Abstract: Methods and systems for modifying at least one synapse of a physicallelectromechanical neural network. A physical/electromechanical neural network implemented as an adaptive neural network can be provided, which includes one or more neurons and one or more synapses thereof, wherein the neurons and synapses are formed from a plurality of nanoparticles disposed within a dielectric solution in association with one or more pre-synaptic electrodes and one or more post-synaptic electrodes and an applied electric field. At least one pulse can be generated from one or more of the neurons to one or more of the pre-synaptic electrodes of a succeeding neuron and one or more post-synaptic electrodes of one or more of the neurons of the physical/electromechanical neural network, thereby strengthening at least one nanoparticle of a plurality of nanoparticles disposed within the dielectric solution and at least one synapse thereof.

Abstract: Methods and systems for constructing biological-scale hierarchically structured cortical statistical memory systems utilizing fabrication technology and meta-stable switching devices. Learning content-addressable memory and statistical random access memory circuits are detailed. Additionally, local and global signal modulation of bottom-up and top-down processing for the initiation and direction of behavior is disclosed.

Abstract: Methods and systems are presented for constructing biological-scale hierarchically structured cortical statistical memory systems using currently available fabrication technology and meta-stable switching devices. Learning content-addressable memory and statistical random access memory circuits are detailed. Additionally, local and global signal modulation of bottom-up and top-down processing for the initiation and direction of behavior is disclosed.

Abstract: Fractal memory systems and methods include a fractal tree that includes one or more fractal trunks. One or more object circuits are associated with the fractal tree. The object circuit(s) can be configured from a plurality of nanotechnology-based components to provide a scalable distributed computing architecture for fractal computing. Additionally, a plurality of router circuits is associated with the fractal tree, wherein one or more fractal addresses output from a recognition circuit can be provided at a fractal trunk by the router circuits.

Abstract: A physical neural network synapse chip and a method for forming such a synapse chip. The synapse chip can be configured to include an input layer comprising a plurality of input electrodes and an output layer comprising a plurality of output electrodes, such that the output electrodes are located perpendicular to the input electrodes. A gap is generally formed between the input layer and the output layer. A solution can then be provided which is prepared from a plurality of nanoconductors and a dielectric solvent. The solution is located within the gap, such that an electric field is applied across the gap from the input layer to the output layer to form nanoconnections of a physical neural network implemented by the synapse chip. Such a gap can thus be configured as an electrode gap. The input electrodes can be configured as an array of input electrodes, while the output electrodes can be configured as an array of output electrodes.

Abstract: A universal logic gate apparatus is disclosed, which include a plurality of self-assembling chains of nanoparticles having a plurality of resistive connections, wherein the plurality of self-assembling chains of nanoparticles comprise resistive elements. A plasticity mechanism is also provided, which is based on a plasticity rule for creating stable connections from the plurality of self-assembling chains of nanoparticles for use with the universal, reconfigurable logic gate. In addition, the universal logic gate can be configured with a cross-bar architecture, where nanoconnections are formed from a columbic-educed mechanical stress contact.

Abstract: A pattern recognition system, comprising a neural network formed utilizing nanotechnology and a pattern input unit, which communicates with the neural network, wherein the neural network processes data input via the pattern input unit in order to recognize data patterns thereof. Such a pattern recognition system can be implemented in the context of a speech recognition system and/or other pattern recognition systems, such as visual and/or imaging recognition systems.

Abstract: An apparatus for maintaining components in neural network formed utilizing nanotechnology is described herein. A connection gap can be formed between two terminals. A solution comprising a melting point at approximately room temperature can be provided, wherein the solution is maintained in the connection gap and comprises a plurality of nanoparticles forming nanoconnections thereof having connection strengths thereof, wherein the solution and the connection gap are adapted for use with a neural network formed utilizing nanotechnology, such when power is removed from the neural network, the solution freezes, thereby locking into place the connection strengths.

Abstract: A temporal summation device can be composed of one or more nanoconnections having an input and an output thereof, wherein an input signal provided to the input causes one or more of the nanoconnection to experience an increase in connection strength thereof over time. Additionally, a voltage divider is formed by the nanoconnection(s) and a resistor connected to the output of the nanoconnection(s), such that the voltage divider provides a voltage at the output the nanoonnection(s) that is in direct proportion to the connection strength of nanoconnection(s). An amplifier is also connected to the voltage divider, wherein when the voltage provided by the voltage divider attains a desired threshold voltage, the amplifier attains a high voltage output thereby providing a temporal summation device thereof.

Abstract: A physical neural network based on nanotechnology, including methods thereof. Such a physical neural network generally includes one or more neuron-like nodes, which are formed from a plurality of interconnected nanoconnections formed from nanoconductors. Each neuron-like node sums one or more input signals and generates one or more output signals based on a threshold associated with the input signal. The physical neural network also includes a connection network formed from the interconnected nanoconnections, such that the interconnected nanoconnections used thereof by one or more of the neuron-like nodes are strengthened or weakened according to an application of an electric field.