Abstract: A multiprocessor architecture utilizing direct memory access (DMA) processors that execute programmed code to feed data to one or more processor cores in advance of those cores requesting data. Stalls of the processor cores are minimized by continually feeding new data directly into the data registers within the cores. When different data is needed, the processor cores can redirect a DMA processor to execute a different feeder program, or to jump to a different point in the feeder program it is already executing. The DMA processors can also feed executable instructions into the instruction pipelines of the processor cores, allowing the feeder program to orchestrate overall processor operations.

Abstract: A router requests a reservation for an egress port prior to dequeuing data from an ingress port data queue. A request is also made for the allocation of a buffer. After the reservation is received and a buffer is allocated, the data is copied the ingress port data queue to the buffer, and an identifier of the buffer is enqueued to an identifier queue of the egress port. After the identifier is dequeued, the data is copied from the buffer to an egress data queue of the egress port, and the buffer is released for reallocation. The buffer can be released prior to completion of the data being copied from the buffer. The queues associated with the egress port determine whether their depths equal or exceed a threshold associated with the respective egress queues. If one or more of the depths does equal or exceed the associated threshold, the granting of reservations for the egress port are postponed.

Abstract: A semiconductor chip with a first processing element, a state machine, a first read first-in first-out (FIFO) memory component, and a second read FIFO memory component. The state machine receives a request from the first processing element for a first value from the first read FIFO memory component and a second value from the second read FIFO memory component. The first processing element may change from an active state to a second state after submitting the read request. The state machine may determine if the first and the second FIFO memory components have data. The first processing element changes back to the active state after the state machine transfers the first and second values to registers.

Abstract: A network on a chip architecture uses hardware queues to distribute multiple-instruction tasks to processors dedicated to performing that task. By repeatedly using the same processors to perform the same task, the frequency at which the processors access memory to retrieve instructions is reduced. If a hardware queue runs dry and a processor is remains idle, the processor will determine which queues have tasks and rededicate to performing a new task that has higher demand, without requiring the intervention of centralized load balancing software or specialized programming.

Abstract: Devices, systems and methods are disclosed for estimating characteristics of noise included in one-dimensional data. For example, a number of data points associated with noise below each of a plurality of thresholds may be determined to calculate a cumulative distribution function. A probability density function may be derived from the cumulative distribution function. A variance may be calculated from the cumulative distribution function and/or the probability density function. The noise may be modeled using the variance and other characteristics determined from the cumulative distribution function and/or the probability density function.

Abstract: Devices, systems and methods are disclosed for reducing noise in input data by performing a hysteresis operation followed by a lateral excitation smoothing operation. For example, an audio signal may be represented as a sequence of feature vectors. A row of the sequence of feature vectors may, for example, be associated with the same harmonic of the audio signal at different points in time. To determine portions of the row that correspond to the harmonic being present, the system may compare an amplitude to a low threshold and a high threshold and select a series of data points that are above the low threshold and include at least one data point above the high threshold. The system may iteratively perform a spreading technique, spreading a center value of a center data point in a kernel to neighboring data points in the kernel, to further reduce noise.

Abstract: An improved virtual memory scheme designed for multi-processor environments that uses processor registers and a small amount of dedicated logic to eliminate the overhead that is associated with the use of page tables. The virtual addressing provides a contiguous virtual address space where the actual real memory is distributed across multiple memories. Locally, within an individual memory, the virtual space may be composed of discontinuous “real” segments or “chunks” within the memory, allowing bad blocks of memory to be bypassed without alteration of the virtual addresses. The delays and additional bus traffic associated with translating from virtual to real addresses are substantially reduced or eliminated.

Abstract: A router requests a reservation for an egress port prior to dequeuing data from an ingress port data queue. A request is also made for the allocation of a buffer. After the reservation is received and a buffer is allocated, the data is copied the ingress port data queue to the buffer, and an identifier of the buffer is enqueued to an identifier queue of the egress port. After the identifier is dequeued, the data is copied from the buffer to an egress data queue of the egress port, and the buffer is released for reallocation. The buffer can be released prior to completion of the data being copied from the buffer. The queues associated with the egress port determine whether their depths equal or exceed a threshold associated with the respective egress queues. If one or more of the depths does equal or exceed the associated threshold, the granting of reservations for the egress port are postponed.

Abstract: A router that requests a reservation for an egress port prior to dequeuing a received packet. A reservation is granted only if there is space on the egress port for at least a maximum size packet. An ingress processor requests allocation of a packet buffer. An allocator grants the packet buffer, but if there are fewer than a threshold number of buffers available, the ingress processor will not accept the grant unless the received packet is to be routed to a port inside the device comprising the router. This conserves the packet buffer(s) for packets destined for locations within the device. After a reservation is obtained and a packet buffer has been accepted, the ingress processor begins dequeuing a received packet from an ingress port queue to the buffer, and provides an identifier of the buffer to an egress processor. The identifier is enqueued by the egress processor. After the identifier is dequeued, the egress processor copies the packet from the buffer to an egress queue and releases the buffer.

Abstract: Combinational circuits in a microprocessor execute instructions to perform permutations on bits of a source byte in a single clock cycle. Each bit in the source byte is permuted in accordance with a permutation map. The only storage within the processor core required to execute these instructions is that needed to hold the source byte, the permutation map, and the result byte. Using the permutation instructions and byte swap instructions, a wide variety of permutation operations can be performed on a word, which in the example circuits is 32 bits.

Abstract: A multiprocessor architecture utilizing direct memory access (DMA) processors that execute programmed code to feed data to one or more processor cores in advance of those cores requesting data. Stalls of the processor cores are minimized by continually feeding new data directly into the data registers within the cores. When different data is needed, the processor cores can redirect a DMA processor to execute a different feeder program, or to jump to a different point in the feeder program it is already executing. The DMA processors can also feed executable instructions into the instruction pipelines of the processor cores, allowing the feeder program to orchestrate overall processor operations.

Abstract: A shared program memory and related components configured to distribute data from a memory block to multiple processors at the same time. An arbiter determines what processors are requesting data from the same memory locations. Data from that memory location is then accessed and sent to the requesting processors so that the data arrives at about the same time to each processor, for example, during the same clock cycle. Such distribution is made possible using a configuration such as a shared data bus with corresponding valid bits for each register or using a multicaster and separate data busses for each processor.

Abstract: Devices, systems and methods are disclosed for reducing noise in input data by performing a hysteresis operation followed by a lateral excitation smoothing operation. For example, an audio signal may be represented as a sequence of feature vectors. A row of the sequence of feature vectors may, for example, be associated with the same harmonic of the audio signal at different points in time. To determine portions of the row that correspond to the harmonic being present, the system may compare an amplitude to a low threshold and a high threshold and select a series of data points that are above the low threshold and include at least one data point above the high threshold. The system may iteratively perform a spreading technique, spreading a center value of a center data point in a kernel to neighboring data points in the kernel, to further reduce noise.

Abstract: In a multi-processor architecture, a plurality of processors share a coprocessor for certain instructions. Each processor may supply the coprocessor with a number of instructions and operands for those instructions. Other operations may be performed while waiting for the results. When the results are needed, the processor may be configured to force synchronization by suspending operations until the results are received. While waiting for the results, the processor enters a low-power state, waking up automatically when the last result waited upon is received.

Abstract: Devices, systems and methods are disclosed for reducing noise in input data by performing a hysteresis operation followed by a lateral excitation smoothing operation. For example, an audio signal may be represented as a sequence of feature vectors. A row of the sequence of feature vectors may, for example, be associated with the same harmonic of the audio signal at different points in time. To determine portions of the row that correspond to the harmonic being present, the system may compare an amplitude to a low threshold and a high threshold and select a series of data points that are above the low threshold and include at least one data point above the high threshold. The system may iteratively perform a spreading technique, spreading a center value of a center data point in a kernel to neighboring data points in the kernel, to further reduce noise.