Patents Assigned to Komatsu Denshi Kinzoku Kabushiki Kaisha
  • Patent number: 8246744
    Abstract: By specifying an initial oxygen concentration in a silicon single crystal and a concentration of thermal donors produced according to a thermal history from 400° C. to 550° C. that the silicon single crystal undergoes during crystal growth, a nucleation rate of oxygen precipitates produced in the silicon single crystal while the silicon single crystal is subjected to a heat treatment is determined. Further, by specifying the heat treatment condition of the silicon single crystal, an oxygen precipitate density and an amount of precipitated oxygen under a given heat treatment condition are predicted by calculation.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: August 21, 2012
    Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Kozo Nakamura, Junsuke Tomioka, Tetsuro Akagi, Shiro Yoshino
  • Patent number: 8080113
    Abstract: An apparatus and a method are provided for accurately analyzing and evaluating a degree of contamination on a chamfered part without mixing impurities from parts other than the chamfered part into chemicals. At a position in which, on a front plane flat part of a semiconductor wafer, a boundary region bordering the chamfered part can come into contact with the chemicals, a radius direction position of the chemicals (a distance between a chemicals center and a wafer center) is determined, scanning is performed in a circumference direction, and the chemicals including impurities are collected. Then, at a position that can be brought into contact with the both chamfered part of the semiconductor wafer and the boundary region, a radius direction position of the chemicals is determined, scanning is performed in the circumference direction and the chemicals including impurities are collected.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: December 20, 2011
    Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Mariko Wakuda, Ichiro Sato
  • Patent number: 8002893
    Abstract: In a Czochralski (CZ) single crystal puller equipped with a cooler and a thermal insulation member, which are to be disposed in a CZ furnace, smooth recharge and additional charge of material are made possible. Further, elimination of dislocations from a silicon seed crystal by use of the Dash's neck method can be performed smoothly. To these ends, there is provided a CZ single crystal puller, wherein a cooler and a thermal insulation member are immediately moved upward away from a melt surface during recharge or additional charge of material or during elimination of dislocations from a silicon seed crystal by use of the Dash's neck method.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: August 23, 2011
    Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Daisuke Ebi, Kentaro Nakamura, Kengo Hayashi, Yoshinobu Hiraishi, Shigeo Morimoto, Hiroshi Monden
  • Publication number: 20090210166
    Abstract: By specifying an initial oxygen concentration in a silicon single crystal and a concentration of thermal donors produced according to a thermal history from 400° C. to 550° C. that the silicon single crystal undergoes during crystal growth, a nucleation rate of oxygen precipitates produced in the silicon single crystal while the silicon single crystal is subjected to a heat treatment is determined. Further, by specifying the heat treatment condition of the silicon single crystal, an oxygen precipitate density and an amount of precipitated oxygen under a given heat treatment condition are predicted by calculation.
    Type: Application
    Filed: January 27, 2005
    Publication date: August 20, 2009
    Applicant: KOMATSU DENSHI KINZOKU KABUSHIKI KAISHA
    Inventors: Kozo Nakamura, Junsuke Tomioka, Tetsuro Akagi, Shiro Yoshino
  • Publication number: 20090170292
    Abstract: A production method for a semiconductor substrate for producing a high quality SGOI substrate 10 in which the dislocation density in a silicon germanium Si1-yGey layer (SGOI layer) formed on an embedded oxide film is reduced and the occurrence of defects is suppressed, by employing the SIMOX method, or a semiconductor substrate. The SGOI substrate is produced by adjusting the composition ratio (x) of the germanium Ge in the silicon germanium Si1-xGex layer prior to the SIMOX method processing, to a composition ratio of a predetermined ratio or less in which the dislocation density in the silicon germanium Si1-yGey layer after the SIMOX method processing becomes a predetermined level or less. Preferably the composition ratio (x) is adjusted to a composition ratio in which the dislocation density in the silicon germanium Si1-yGey layer (SGOI layer) after the SIMOX method processing becomes 106 cm?2 or less.
    Type: Application
    Filed: July 27, 2005
    Publication date: July 2, 2009
    Applicant: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Masato Imai, Yoshiji Miyamura
  • Publication number: 20090156101
    Abstract: A polishing apparatus comprises a polishing plate (24), an abrasive cloth (25) attached to the surface of the polishing plate (24), a chuck (19) for holding and pressing one surface of a wafer (39) against the abrasive cloth (25), and a circular retaining ring (23) concentrically arranged on the periphery of the chuck (19). The retaining ring (23) is rotatable and vertically movable with respect to the chuck (19), and is pressed against the abrasive cloth (25) during the lapping step. The retaining ring (23) is lifted upward during the final polishing step, thereby preventing lapping grains from being brought into the final polishing stage. Accordingly, lapping and final polishing can be successively conducted using the same polishing head. With this structure, cost cutting of the apparatus can be realized, since lapping and final polishing are successively conducted using the same polishing head without bringing the lapping grains used for lapping into the final polishing stage.
    Type: Application
    Filed: February 13, 2009
    Publication date: June 18, 2009
    Applicant: KOMATSU DENSHI KINZOKU KABUSHIKI KAISHA
    Inventors: Masamitsu Kitahashi, Toshiyuki Kamei, Hidetoshi Takeda, Hiroyuki Tokunaga, Tomoaki Tajiri
  • Publication number: 20080311019
    Abstract: In a Czochralski (CZ) single crystal puller equipped with a cooler and a thermal insulation member, which are to be disposed in a CZ furnace, smooth recharge and additional charge of material are made possible. Further, elimination of dislocations from a silicon seed crystal by use of the Dash's neck method can be performed smoothly. To these ends, there is provided a CZ single crystal puller, wherein a cooler and a thermal insulation member are immediately moved upward away from a melt surface during recharge or additional charge of material or during elimination of dislocations from a silicon seed crystal by use of the Dash's neck method.
    Type: Application
    Filed: October 31, 2007
    Publication date: December 18, 2008
    Applicant: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Hiroshi Inagaki, Shigeki Kawashima, Makoto Kamogawa, Toshirou Kotooka, Toshiaki Saishoji, Daisuke Ebi, Kentaro Nakamura, Kengo Hayashi, Yoshinobu Hiraishi, Shigeo Morimoto, Hiroshi Monden, Tadayuki Hanamoto, Tadashi Hata
  • Publication number: 20080311021
    Abstract: In a Czochralski (CZ) single crystal puller equipped with a cooler and a thermal insulation member, which are to be disposed in a CZ furnace, smooth recharge and additional charge of material are made possible. Further, elimination of dislocations from a silicon seed crystal by use of the Dash's neck method can be performed smoothly. To these ends, there is provided a CZ single crystal puller, wherein a cooler and a thermal insulation member are immediately moved upward away from a melt surface during recharge or additional charge of material or during elimination of dislocations from a silicon seed crystal by use of the Dash's neck method.
    Type: Application
    Filed: October 31, 2007
    Publication date: December 18, 2008
    Applicant: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Hiroshi Inagaki, Shigeki Kawashima, Makoto Kamogawa, Toshirou Kotooka, Toshiaki Saishoji, Daisuke Ebi, Kentaro Nakamura, Kengo Hayashi, Yoshinobu Hiraishi, Shigeo Morimoto, Hiroshi Monden, Tadayuki Hanamoto, Tadashi Hata
  • Patent number: 7374614
    Abstract: The method for manufacturing a single crystal semiconductor achieves an object to reduce the impurity concentration nonuniformity within a semiconductor wafer plane and thus to improve the wafer planarity by introducing an impurity into the single crystal semiconductor more uniformly during the pulling of the single crystal semiconductor from a melt. In the course of pulling the single crystal semiconductor (6), the rotating velocity (?2) of the single crystal semiconductor (6) being pulled is adjusted to a predetermined value or higher, and a magnetic field having a strength in a predetermined range is applied to the melt (5). Particularly, the crystal peripheral velocity is adjusted to 0.126 m/sec or higher, and M/V1/3 is adjusted to 35.5?M/V1/3?61.3. More desirably, the crystal peripheral velocity is adjusted to 0.141 m/sec or higher, and M/V1/3 is adjusted to 40.3?M/V1/3?56.4.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: May 20, 2008
    Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Masafumi Ura, Hidetoshi Kurogi, Toshiharu Yubitani, Noboru Furuichi
  • Patent number: 7329317
    Abstract: The present invention is to produce a silicon crystal wherein the boron concentration in the silicon crystal and the growth condition V/G are controlled so that the boron concentration in the silicon crystal is no less than 1×1018 atoms/cm3 and the growth condition V/G falls within the epitaxial defect-free region ?2 whose lower limit line LN1 is the line indicating that the growth rate V gradually drops as the boron concentration increases. A silicon wafer is also produced wherein the boron concentration in the silicon crystal and the growth condition V/G are controlled so as to include at least the epitaxial defect region ?1, and both the heat treatment condition and the oxygen concentration of the silicon crystal are controlled so that no OSF nuclei grow to OSFs.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: February 12, 2008
    Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Susumu Maeda, Hiroshi Inagaki, Shigeki Kawashima, Shoei Kurosaka, Kozo Nakamura
  • Publication number: 20070256625
    Abstract: In a Czochralski (CZ) single crystal puller equipped with a cooler and a thermal insulation member, which are to be disposed in a CZ furnace, smooth recharge and additional charge of material are made possible. Further, elimination of dislocations from a silicon seed crystal by use of the Dash's neck method can be performed smoothly. To these ends,there is provided a CZ single crystal puller, wherein a cooler and a thermal insulation member are immediately moved upward away from a melt surface during recharge or additional charge of material or during elimination of dislocations from a silicon seed crystal by use of the Dash's neck method.
    Type: Application
    Filed: May 31, 2007
    Publication date: November 8, 2007
    Applicant: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Hiroshi Inagaki, Shigeki Kawashima, Makoto Kamogawa, Toshirou Kotooka, Toshiaki Saishoji, Daisuke Ebi, Kentaro Nakamura, Kengo Hayashi, Yoshinobu Hiraishi, Shigeo Morimoto, Hiroshi Monden, Tadayuki Hanamoto, Tadashi Hata
  • Publication number: 20070204881
    Abstract: An apparatus and a method are provided for accurately analyzing and evaluating a degree of contamination on a chamfered part without mixing impurities from parts other than the chamfered part into chemicals. At a position in which, on a front plane flat part of a semiconductor wafer, a boundary region bordering the chamfered part can come into contact with the chemicals, a radius direction position of the chemicals (a distance between a chemicals center and a wafer center) is determined, scanning is performed in a circumference direction, and the chemicals including impurities are collected. Then, at a position that can be brought into contact with the both chamfered part of the semiconductor wafer and the boundary region, a radius direction position of the chemicals is determined, scanning is performed in the circumference direction and the chemicals including impurities are collected.
    Type: Application
    Filed: June 28, 2005
    Publication date: September 6, 2007
    Applicant: Komatsu DEnshi Kinzoku Kabushiki Kaisha
    Inventors: Mariko Wakuda, Ichiro Sato
  • Publication number: 20070184662
    Abstract: The carrier (10) for double-side polishing has a base material 10a the material of which is stainless steel (SUS) , for example, as is before, and the base material 10a is coated with a coating layer 10b of a material having a hardness higher than that of the base material 10a. The coating layer 10b is desirably coated uniformly without variations in thickness and not warped easily, and the material for the coating layer 10b of the double-side polishing carrier 10 is desirably any one selected from diamond-like carbon, a nitride film, a sapphire film and a titanium nitride film. For production of the double-side polishing carrier 10, a double-side polishing carrier 10? having been used for polishing is prepared first. The used carrier 10? is coated with the coating layer 10b. The invention can suppress the progress of abrasion of the double-side polishing carrier, and can provide satisfactory thickness accuracy, film thickness distribution accuracy, and surface roughness.
    Type: Application
    Filed: June 23, 2005
    Publication date: August 9, 2007
    Applicant: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Kenji Yamashita, Yukio Oono, Yuuji Sugimoto
  • Patent number: 7235128
    Abstract: A process for producing a single-crystal semiconductor and an apparatus therefor. A single-crystal semiconductor of large diameter and large weight can be lifted with the use of existing equipment not having any substantial change thereto while not influencing the oxygen concentration of single-crystal semiconductor and the temperature of melt and while not unduly raising the temperature of seed crystal. In particular, the relationship (L1, L2, L3) between the allowable temperature difference (?T) and the diameter (D) of seed crystal (14) is preset so that the temperature difference between the seed crystal (14) at the time the seed crystal (14) is immersed in the melt and the melt (5) falls within the allowable temperature difference (?T) at which dislocations are not introduced into the seed crystal (14). In accordance with the relationship (L1, L2, L3), the allowable temperature difference (?T) corresponding to the diameter (D) of seed crystal (14) to be immersed in the melt is determined.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: June 26, 2007
    Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Susumu Maeda, Hiroshi Inagaki, Shigeki Kawashima, Shoei Kurosaka, Kozo Nakamura
  • Publication number: 20070131158
    Abstract: The method for manufacturing a single crystal semiconductor achieves an object to reduce the impurity concentration nonuniformity within a semiconductor wafer plane and thus to improve the wafer planarity by introducing an impurity into the single crystal semiconductor more uniformly during the pulling of the single crystal semiconductor from a melt. In the course of pulling the single crystal semiconductor (6), the rotating velocity (?2) of the single crystal semiconductor (6) being pulled is adjusted to a predetermined value or higher, and a magnetic field having a strength in a predetermined range is applied to the melt (5). Particularly, the crystal peripheral velocity is adjusted to 0.126 m/sec or higher, and M/V1/3 is adjusted to 35.5?M/V1/3?61.3. More desirably, the crystal peripheral velocity is adjusted to 0.141 m/sec or higher, and M/V1/3 is adjusted to 40.3?M/V1/3?56.4.
    Type: Application
    Filed: February 18, 2005
    Publication date: June 14, 2007
    Applicant: KOMATSU DENSHI KINZOKU KABUSHIKI KAISHA
    Inventors: Masafumi Ura, Hidetoshi Kurogi, Toshiharu Yubitani, Noboru Furuichi
  • Publication number: 20070068448
    Abstract: A single crystal semiconductor manufacturing apparatus in which the concentration of oxygen in a single crystal semiconductor is controlled while pulling up a single crystal semiconductor such as single crystal silicon by the CZ method, a single crystal semiconductor manufacturing method, and a single crystal ingot manufactured by the method are disclosed. The natural convection (20) in the melt (5) in a quartz crucible (3) is controlled by regulating the temperatures at a plurality of parts of the melt (5). A single crystal semiconductor (6) can have a desired diameter by regulating the amount of heat produced by heating means (9a) on the upper side. Further the ratio between the amount of heat produced by the upper-side heating means (9a) and that by the lower-side heating means (9b) is adjusted to vary the process condition. In the adjustment, the amount of heat produced by the lower-side heating means (9b) is controlled to a relatively large proportion.
    Type: Application
    Filed: November 29, 2006
    Publication date: March 29, 2007
    Applicant: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Yutaka Shiraishi, Jyunsuke Tomioka, Takuji Okumura, Tadayuki Hanamoto, Takehiro Komatsu, Shigeo Morimoto
  • Publication number: 20070051303
    Abstract: A semiconductor single crystal manufacturing apparatus capable of lowering the local deterioration of a wire under high temperature atmosphere in the furnace of a chamber, wherein a crucible (24) in which silicon melt (28) is filled is installed in the furnace of the chamber (22), a pull-chamber (23) is disposed above the chamber (22), and a seed holder (32) lifting between the inside of the pull-chamber (23) and the inside of the furnace is suspended by a wire (50) through a coupling member (31). A collar (52) is fitted to the wire (50) so that, when the seed holder (32) is positioned to touch the melt, the exposed portion of the wire (50) near the tip thereof becomes a specified temperature or below under the high temperature atmosphere in the furnace.
    Type: Application
    Filed: October 13, 2004
    Publication date: March 8, 2007
    Applicant: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventor: Toshirou Umeki
  • Publication number: 20070017901
    Abstract: Disclosed are a method and apparatus for etching disk-shaped members, especially a method and apparatus for etching semiconductor wafers. In a method wherein wafers (30) are rotated and etched in an etching chamber (12) which is filled with an etching solution, a non-rotating cell plate (26) is disposed between two rotating wafers (30). In an etching apparatus wherein multiple wafers (30) are supported and rotated by a rod (16), the cell plate (26) is disposed between each two wafers (30). The cell plate (26) has a surface area roughly equivalent to that of the wafer (30).
    Type: Application
    Filed: July 29, 2004
    Publication date: January 25, 2007
    Applicant: KOMATSU DENSHI KINZOKU KABUSHIKI KAISHA
    Inventors: Tadamitsu Miyazaki, Kazuya Hirayama, Hisaya Fukunaga, Hiroyasu Futamura
  • Patent number: 7160386
    Abstract: A single crystal semiconductor manufacturing apparatus in which the concentration of oxygen in a single crystal semiconductor is controlled while pulling up a single crystal semiconductor such as single crystal silicon by the CZ method, a single crystal semiconductor manufacturing method, and a single crystal ingot manufactured by the method are disclosed. The natural convection (20) in the melt (5) in a quartz crucible (3) is controlled by regulating the temperatures at a plurality of parts of the melt (5). A single crystal semiconductor (6) can have a desired diameter by regulating the amount of heat produced by heating means (9a) on the upper side. Further the ratio between the amount of heat produced by the upper-side heating means (9a) and that by the lower-side heating means (9b) is adjusted to vary the process condition. In the adjustment, the amount of heat produced by the lower-side heating means (9b) is controlled to a relatively large proportion.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: January 9, 2007
    Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Yutaka Shiraishi, Jyunsuke Tomioka, Takuji Okumura, Tadayuki Hanamoto, Takehiro Komatsu, Shigeo Morimoto
  • Patent number: 7147710
    Abstract: There is described a method which enables stable manufacture of a high-quality, ultra-thin epitaxial silicon wafer, as well as an epitaxial silicon wafer capable of bearing shipment manufactured by the method. A method of manufacturing an epitaxial silicon wafer having an ultra-thin epitaxial film, by means of forming an epitaxial film on a silicon wafer after having annealed the silicon wafer, includes the steps of: sufficiently smoothing COPs formed in the surface of the silicon wafer by means of appropriately setting annealing conditions according to an size of COPs in the vicinity of a surface of the silicon wafer; and forming an epitaxial film through epitaxial growth.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: December 12, 2006
    Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Kazuya Togashi, Masayoshi Danbata, Kuniaki Arai, Kaori Matsumoto