Patents Assigned to Komatsu Electronic Metals Co., Ltd.
  • Patent number: 5853480
    Abstract: An apparatus and a method for fabricating a single-crystal semiconductor by means of a CZ method are provided for improving the quality through modification of the thermal cycle of a pulled single-crystal semiconductor. The apparatus includes a ring-shaped after heater which is capable of elevation. The method decreases the temperature gradient to smaller than 20.degree. C./cm, and preferably under 15.degree. C./cm, when the pulled single-crystal semiconductor is cooled from 1200.degree. C. to 1000.degree. C. The after heater therefore heats the single-crystal semiconductor where there is a temperature of 100.degree.-300.degree. C. lower than the range of 1200.degree.-1000.degree. C. A thermal baffle (or shield) is provided to retain a temperature gradient of larger than 20.degree. C./cm when the single-crystal semiconductor is within the temperature range between the melting point and 1250.degree. C.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: December 29, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Toshimichi Kubota, Toshiro Kotooka, Makoto Kamogawa
  • Patent number: 5851924
    Abstract: A method for fabricating a semiconductor wafer to reduce the number of processing steps and produce low-cost wafers in a short time is disclosed. The method involves surface grinding both the front surface and back surface of a single-crystal silicon wafer which has been sliced from a rod and chamfered. In the surface grinding step, the size numbers of abrasive grains are larger than #2000 for front surface grinding, and smaller than #600 for back surface grinding. The front surface is then chemical polished as a mirror surface which satisfies the requirement of a later photolithography step. Moreover, a deformation layer formed on the back surface of the semiconductor wafer is partially etched and left to provide an extrinsic gettering function. An epitaxial layer can be formed on the front surface to make the wafer an epitaxial wafer. The method of the present invention requires fewer process steps as compared with conventional methods, thereby reducing manufacturing time and cost.
    Type: Grant
    Filed: December 11, 1996
    Date of Patent: December 22, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Atsuo Nakazawa, Yuuichirou Mukai, Tomoaki Tajiri
  • Patent number: 5849139
    Abstract: A method of sticking a semiconductor wafer and its sticking equipment. The semiconductor wafer can be flat and efficiently stuck on a plate. The semiconductor wafer, which has its inner surface coated with an adhesive, is tiltedly configured to permit raising a circumference to a height of Ah and located the wafer above a sticking position on the plate. The semiconductor wafer is pressed by a lower end of a stamp-press to be parallel to a surface of the plate. Then a vacuum chuck (2) stops sucking to release the semiconductor wafer from a transporting arm, and the transporting arm is moved away. The stamp-press is moved downward to press a whole surface of the semiconductor wafer.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: December 15, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Kiyoharu Miyakawa, Osamu Morikawa
  • Patent number: 5849603
    Abstract: A surface processing method for evaluating semiconductor substrate is intended to clean a semiconductor substrate, which has the surface of a silicon layer exposed by removing the epitaxial layer by an acid mixture, by buffered HF and then to perform SC-1 cleaning. Placing the substrate for about 2 hours after the processing, then the varying rate of the SPV value is quite stable at about 5%, so that the minor carrier diffusion length can be measured with high precision. Furthermore, the lead time of evaluating a semiconductor substrate can be significantly reduced over the prior-art method.
    Type: Grant
    Filed: April 2, 1996
    Date of Patent: December 15, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hirotaka Kato, Yuji Sato, Kei Matsumoto
  • Patent number: 5849636
    Abstract: A method processes a semiconductor wafer by etching the wafer, which has been smoothed by rough lapping, with alkaline solution. A rod is sliced into a plurality of wafers. The peripheral edges of the wafers are chamfered. The processed strain layers over the wafers due to chamfering are smoothed and planarized. The processed strain layers are then removed by etching with alkaline solution. The etched wafers are mirror polished. Lastly, the mirror-polished wafers are cleaned.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: December 15, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Takamitsu Harada, Kouichi Imura, Hisaya Fukunaga, Masahiko Maeda
  • Patent number: 5845630
    Abstract: A process for fabricating a semiconductor wafer and an apparatus for chamfering a semiconductor ingot are provided to precisely perform the chamfering together and reduce significantly the cutting and chamfering time. The semiconductor ingot 2 is rotated with respect to the central axis C while the circumferential surface 21 of the rotating ingot 2 is brought in contact with the uneven surface 11 of a grindstone 1. The circumferential surface of the ingot is chamfered in accordance with the uneven surface 11 of the grindstone 1. A wiresaw is used to cut the semiconductor ingot 2 to obtain the sliced wafers 3.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: December 8, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventor: Naoki Yamada
  • Patent number: 5824153
    Abstract: An apparatus for holding a single-crystal semiconductor ingot which is stored in a pulling chamber of a single-crystal semiconductor pulling apparatus is disclosed. The apparatus includes a spindle; a base installed on the spindle and movable along the spindle; a pair of arms for holding the single-crystal semiconductor ingot; means for driving the arms; a pair of sensors for detecting the distance between the ingot and the arms; and a controller for driving the arms to the ingot according to the sensors; when each of the arms is detected to have a predetermined distance from the ingot, the controller stopping the movement of the arm; when both the arms have the predetermined distance to the ingot, the controller driving simultaneously both the arms to the ingot surface, thereby holding the ingot.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: October 20, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd
    Inventors: Ayumi Suda, Yoshinobu Hiraishi, Koichi Shimomura
  • Patent number: 5824152
    Abstract: In the manufacture of a single crystal using a semiconductor single-crystal pulling apparatus equipped with a radiation screen, the time of passage of the single crystal through the high-temperature region of 1050.degree. C. and above is made to be long and the time of passage of the single crystal through the temperature region of about 900.degree. C.-500.degree. C. is made to be short. The semiconductor single-crystal pulling apparatus is so constructed that a radiation screen comprises an upper screen of 3-layer construction consisting of a heat-insulating member made of graphite or ceramics fiber clad with outer members made of graphite and a lower screen 3 of single-layer construction made of graphite, quartz or fine ceramics. Radiant heat from the molten liquid heats the lower part of single crystal as it passes through lower screen, thereby prolonging its period of passage through the high-temperature region.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: October 20, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Toshimichi Kubota, Toshiro Kotooka, Toshiaki Saishoji, Tetsuhiro Iida
  • Patent number: 5821166
    Abstract: method of manufacturing semiconductor wafers, which can prevent the pendent surface phenomenon during the mirror polishing of the wafers and can enhance the flatness of the mirror polished surfaces. The method of manufacturing semiconductor wafers according to this invention includes slicing ingots into wafers, chamfering the peripheral edge portions of the wafers, lapping the sliced surfaces of the wafers, grinding the lapped surfaces of the wafers to form a gradual concave shape, mirror polishing the ground surfaces of the wafers, and finally cleaning the mirror polished wafers.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: October 13, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hirofumi Hajime, Toshiharu Yubitani
  • Patent number: 5814240
    Abstract: A method for polishing a semiconductor wafer, which can prevent from occurring a sloped edge at a peripheral portion of the semiconductor wafer and produce a semiconductor wafer of high-flatness, is provided.The polishing method utilizes a polishing block consisting of a ceramic plate 11, a backing pad 12 and a template 13. The backing pad 12 has a larger compression rate than that of the polishing cloth 2. The polishing block 1 is mounted on a semiconductor wafer 3. The semiconductor wafer 3 is pressed against the polishing cloth 2 to perform the polishing.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: September 29, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventor: Junichi Yamashita
  • Patent number: 5799644
    Abstract: A semiconductor single crystal ingot cutting jig is shaped as a cylinder having a diameter approximately equal to an ingot diameter. A recess is provided at one end of the jig for receiving a head (or tail) of the ingot. An adhesive is provided in the recess so as to adhere the ingot to the jig when the head (or tail) of the ingot is inserted into the recess. Then, the ingot is fixed on a bed of a band-saw slicing machine. The head (or tail) of the ingot is fixed on the jig and thus will not overturn at the time just before finishing the cutting or at the end of cutting. This can prevent a blade of a band saw slicing machine from being damaged.
    Type: Grant
    Filed: October 22, 1996
    Date of Patent: September 1, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventor: Kouji Nishida
  • Patent number: 5800612
    Abstract: A single-crystal semiconductor pulling apparatus improves the crystallization rate by reinforcing the physical strength of the Dash's neck portion, and eliminate the process time difference depending on the experiences of operators. The single-crystal semiconductor pulling apparatus, which is according to the Czochralski method, includes controller for automatically controlling the pulling rate of a seed crystal and a melt temperature. The controller modifies a target value of a diameter of a crystal grown from the seed which is immersed from a first value to a second value. The first value is for ensuring dislocation-free state, while the second value is for retaining physical strength of the crystal. Furthermore, the controller is provided with the function of judging the crystal to be in dislocation-free state.
    Type: Grant
    Filed: February 6, 1997
    Date of Patent: September 1, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Koichi Shimomura, Yoshinobu Hiraishi, Taizou Miyamoto
  • Patent number: 5785757
    Abstract: The present invention provides a method and an apparatus for fabricating a single-crystal semiconductor by means of the CZ method in which the oxygen concentration in the single-crystal semiconductor is controlled within an acceptable range. The apparatus comprises a regulating cylinder concentrically covering the single-crystal semiconductor which is pulled from a melt in a crucible; a main chamber for isolating the growing single-crystal semiconductor from external atmosphere; and a falling gas introducing means on top of the main chamber for introducing an inert gas into the main chamber. The apparatus is characterized in that a whirling gas introducing means on a circumferential portion of the main chamber introduces an whirling inert gas into the main chamber in a tangential direction to the side walls of the main chamber and the regulating cylinder.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: July 28, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventor: Yoshinobu Hiraishi
  • Patent number: 5770511
    Abstract: The present invention, a silicon-on-insulator (SOI) substrate and its fabrication method, is suited to the wafer-bonding method. A pre-oxidation treatment accompanying the oxidation treatment and the adhesive thermal treatment to prevent metal impurities from polluting semiconductor wafers. Before an oxide layer is thermally grown on one wafer or after two bonded wafers are subjected to a adhesive thermal treatment at a temperature T1, the pre-oxidation treatment is performed at a temperature of T2, which satisfies the relation equation of T1-300.ltoreq.T2.ltoreq.T1-100 (.degree.C.). Water steam, pure oxygen, or diluted oxygen, is conducted into the furnace, in which the pre-oxidation treatment is performed in an oxidation ambient. Accordingly, an oxide film having a predetermined thickness is formed on the surface of the SOI substrate serving as a barrier for preventing metal impurities, such as Fe, Cr, or the like, from invading the substrate and degrading the electrical characteristics thereof.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: June 23, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Kei Matsumoto, Hirotaka Kato, Hiroshi Furukawa
  • Patent number: 5766347
    Abstract: An apparatus for fabricating a semiconductor single crystal, which make it possible to reduce the oxygen concentration of a pulling single crystal, to steadily dissolve the polysilicon material received in a crucible, and to minimize the cost and installation space, is provided.The hollow cylindrical resistance heater of the apparatus, which co-axially surrounds a crucible, is provided with a ring-shaped slit excluding the location where at least two electrodes are formed, in a direction substantially perpendicular to the axial direction so as to divide the heater into an upper heating portion and a lower heating portion, and is provided with a plurality of vertical slits formed on the upper heating portion and the lower heating portion respectively, in a direction substantially parallel to the axial direction, wherein each vertical slit formed on the upper heating portion does not align with each vertical slit formed on the lower heating portion.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: June 16, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Koichi Shimomura, Yoshinobu Hiraishi, Mitsunori Kawabata
  • Patent number: 5756399
    Abstract: The present invention provides a process for making a semiconductor wafer, including slicing an ingot to obtain wafers; surface-grinding both sides of each of the wafers; etching the wafers with an alkaline solution; chamfering the peripheral portion of each of the wafers; both-side polishing the wafers for mirror processing ; cleaning both sides of each of the wafers to remove the particles attached to the sides; and drying and cleaning the wafers. By employing the present process, the time for polishing the wafer can be shortened, and the semiconductor wafer can be made effectively.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: May 26, 1998
    Assignee: Komatsu Electronic Metals Co. Ltd.
    Inventors: Hirofumi Hajime, Toshiharu Yubitani
  • Patent number: 5747364
    Abstract: A method of making semiconductor wafers can prevent processing strain on peripheral portions of wafers caused by non-wax polishing using a template. This involves mirror chamfering or etching the peripheral portions of the wafers after the non-wax polishing step.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: May 5, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Nobuyuki Akiyama, Fumitaka Kai, Masahiko Maeda, Hirofumi Hajime, Naoki Yamada
  • Patent number: 5744380
    Abstract: There is provided a high quality epitaxial water on which the density of microscopic defects in the epitaxial layer is reduced to keep the GOI thereof sufficiently high and to reduce a leakage current at the P-N junction thereof when devices are incorporated, to thereby improve the yield of such devices. In an epitaxial wafer obtained by forming an epitaxial layer on a substrate, the density of IR laser scatterers is 5.times.10.sup.5 pieces/cm.sup.3 or less throughout the epitaxial layer.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: April 28, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Noriyuki Uemura, Hisami Motoura, Masashi Nishimura, Mitsuo Kohno
  • Patent number: 5742176
    Abstract: An evaluation method of a silicon wafer by correctly calculating the Fe--B concentration is disclosed. Even when the SPV method is utilized, the over-estimated Fe--B concentration in silicon wafers containing oxygen-precipitation defects can be avoided. Diffusion lengths Lb and La of minority carriers in a P-type silicon wafer before and after an activation step are measured by the SPV method. A value of (Lb--La)/Lb calculated from La and Lb is compared with a constant C which is read from the plot of Lb vs. (Lb--La). If (Lb--La)/Lb is smaller than constant C, the concentration calculation is terminated since there are oxygen-precipitation defects in the silicon wafer. The calculation is carried out for silicon wafers containing no oxygen-precipitation defects, and is based on the formula of Fe--B concentration (cm.sup.-3).apprxeq.1.times.10.sup.16 (La.sup.-2 --Lb.sup.-2).
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: April 21, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hirotaka Kato, Kei Matsumoto
  • Patent number: 5725100
    Abstract: A semiconductor wafer case provides high resistance to vibration. The semiconductor wafer can be easily accessed from the case. The semiconductor wafer case includes a case body and a holder in which blade-type presser feet are provided. An end of each of the presser feet has a V-shaped cross-section. Spaces are provided between presser feet (32a, 33a) and presser feet (32b, 33b). Two holders of the same shape are provided at opposite sides of the case body so that the holders can hold the semiconductor wafer horizontally.
    Type: Grant
    Filed: November 14, 1996
    Date of Patent: March 10, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventor: Naoki Yamada