Patents Assigned to Komatsu Electronics Metals Co., Ltd.
  • Patent number: 5725660
    Abstract: A semiconductor single crystal growing apparatus is vertically and telescopically provided with a seed holder. The seed holder comprises a seed-holding member for holding a seed and a suspending bolt for bolting the seed-holding member. The front end of the seed coincides with a datum point when the seed holder is moved to a top dead point.
    Type: Grant
    Filed: November 29, 1996
    Date of Patent: March 10, 1998
    Assignee: Komatsu Electronic Metals Co. Ltd.
    Inventor: Yoshinobu Hiraishi
  • Patent number: 5708365
    Abstract: A simple method for evaluating the dielectric breakdown of an oxide layer on a silicon wafer is disclosed. The SPV method is utilized to measure a diffusion length L.sub.on of minority carriers when the silicon wafer is illuminated by white light from another source and a diffusion length L.sub.off of the minority carriers when the silicon wafer is not illuminated by white light from another source. A diffusion length L.sub.safe, which is determined by trap sites in the silicon wafer, is calculated from an equation L.sub.safe =(L.sub.off.sup.-2 -L.sub.on.sup.-2).sup.-1/2. Since L.sub.safe has a strong correlation with the dielectric breakdown of the oxide layer, the dielectric breakdown of the oxide layer can be easily evaluated by L.sub.safe during the fabrication of the silicon wafer.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: January 13, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Shiro Yoshino, Seiichi Shimura, Mitsuo Kono
  • Patent number: 5704974
    Abstract: When a Si single crystal 8 is pulled up from a melt 6 received in a crucible 2, the state of eddy flows generated in the melt 6 is judged from the temperature distribution of the melt at the surface. According to the result of judgement, the gas, i.e. N.sub.2, Xe or Kr, which causes extraoridnary deviation in the density of a melt 6 is added to an atmospheric gas, so as to keep the eddy flows under unstabilized condition. The effect of said gas is typical in the case of crystal growth from the melt to which a dopant such as Ca, Sb, Al, As or In having the effect to suppress the extraordinary deviation in the density is added. Since the single crystal is pulled up from the melt held in the temperature-controlled condition at the surface, impurity distribution and oxygen distribution are made uniform along the direction of crystal growth. A single crystal obtained in this way has highly-stabilized quality.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: January 6, 1998
    Assignees: Research Development Corporation of Japan, Sumitomo Sitix Corporation, Toshiba Ceramics Co., Ltd., Nippon Steel Corporation, Komatsu Electronic Metals Co., Ltd., Mitsubishi Materials Corporation
    Inventors: Koji Izunome, Souroku Kawanishi, Shinji Togawa, Atsushi Ikari, Hitoshi Sasaki, Shigeyuki Kimura
  • Patent number: 5700321
    Abstract: The object of the present invention affords a method of feeding dopant and a dopant composition used therein for easily preparing single crystals having a desired doping concentration during semiconductor substrate fabrication.In accordance with the present invention, a water solution containing oxides of the dopant is first added to the liquid containing colloidal silica. The colloidal silica can adsorb the oxides of the dopant to form a dopant composition. Around rod-shaped polysilicon, that is polysilicon rod, the dopant composition is discontinuously coated on the periphery of the polysilicon rods spaced at constant intervals and then dried. When the polysilicon rods are melted in an apparatus for manufacturing single crystals by a heater, dopant is protected by the glassed silica without evaporation. Accordingly, the dopant can be provided at a predetermined concentration to sustain the grown single crystals having a doping concentration as required.
    Type: Grant
    Filed: July 26, 1996
    Date of Patent: December 23, 1997
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventor: Keishi Niikura
  • Patent number: 5700320
    Abstract: When a B or P-doped Si single crystal is pulled up from a B or P-doped melt by the Czochralski method, an element such as Ga, Sb or In having the effect to reduce the heat expansion coefficient of said melt at a temperature near the melting point is added to said melt. The additive element stabilizes the temperature condition of crystal growth so as to control the generation of eddy flows just below the interface of crystal growth.When a Ga or Sb-doped Si single crystal is pulled up from a Ga or Sb-doped melt, an element such as B or P having the effect to increase the heat expansion coefficient of said melt at a temperature near the melting point is added. The agitation of the melt just below the interface of crystal growth is accelerated by the addition of B or P, so as to assure the growth of a Si single crystal from the melt having impurity distribution made uniform along the radial direction.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: December 23, 1997
    Assignees: Research Development Corporation of Japan, Sumitomo Sitix Corporation, Toshiba Ceramics Co., Ltd., Nippon Steel Corporation, Komatsu Electronic Metals Co., Ltd., Mitsubishi Materials Corporation
    Inventors: Koji Izunome, Souroku Kawanishi, Shinji Togawa, Atsushi Ikari, Hitoshi Sasaki, Shigeyuki Kimura
  • Patent number: 5690742
    Abstract: A susceptor for an epitaxial growth apparatus, which can maximize the surface utilization of the susceptor and increase the number of semiconductor wafers in a single run. The shape of the pocket for loading a semiconductor wafer at a specific position is similar to and slightly larger than that of the semiconductor wafer with an orientation flat. In addition, the pocket is so located that the orientation flat will be close to adjacent semiconductor wafers. Therefore, compared with the conventional one, the distance between centers of adjacent pockets can be reduced and the total number of the semiconductor wafers that can be loaded on the susceptor in the same surface area can be increased. After the epitaxial growth process, the semiconductor wafers can be removed from the susceptor using the notchs on the periphery of the pockets.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: November 25, 1997
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Kazuro Ogata, Kazuhisa Iwanaga
  • Patent number: 5683504
    Abstract: When a single crystal is pulled up from a melt, the difference .DELTA.T between temperatures at the bottom of a crucible and at the interface of crystal growth is controlled so as to hold the Rayleigh constant defined by the formula of:R a=g.multidot..beta..multidot..DELTA.T.multidot.L/.kappa..multidot..nu.within the range of 5.times.10.sup.5 -4.times.10.sup.7, wherein g represents the acceleration of gravity, .beta. the volumetric expansion coefficient of the melt, L the depth of the melt, .kappa. thermal diffusivity and .nu. the kinematic viscocity. Since the convection mode of the melt at the interface of crystal growth is constantly held in the region of soft turbulence, a single crystal is grown under the stabilized temperature condition without the transfer of the impurity distribution in the melt into the growing single crystal.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: November 4, 1997
    Assignees: Research Development Corporation of Japan, Sumitomo Sitix Corporation, Toshiba Ceramics Co., Ltd., Nippon Steel Corporation, Komatsu Electronic Metals Co., Ltd., Mitsubishi Materials Corporation
    Inventors: Koji Izunome, Souroku Kawanishi, Shinji Togawa, Atsushi Ikari, Hitoshi Sasaki, Shigeyuki Kimura
  • Patent number: 5681758
    Abstract: A method of supplying raw material for fabricating semiconductor single crystal according to the continuously charged method provides an inventive method to overcome the problems of the raw material being charged either insufficiently or excessively, and to charge the raw material steadily. According to the inventive method, the raw material of two polysilicon bars is melted simultaneously and flows to the crucible. By calculating the difference between the weight of the growing single crystal and that of the molten raw material, the insufficiency or excess of the raw material charged is obtained, thereby inducing the equivalent regulation. Further, the coordinates of the tips of the raw material of two polysilicon bars while molten is taken to control the power of the two heaters which melt the polysilicon bars respectively for keeping the coordinates of the two tips in a constant position.
    Type: Grant
    Filed: November 4, 1996
    Date of Patent: October 28, 1997
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventor: Yutaka Shiraishi
  • Patent number: 5679476
    Abstract: An epitaxial wafer capable of removing impurities and oxide layers thereon having a high dielectric strength is disclosed. A substrate wafer 1 in which laser-scattering centers have a density of higher than 5.times.10.sup.6 /cm.sup.3 is provided. An epitaxial layer 3 is formed by epitaxial growth on a completely clean surface of the substrate. The surface of the epitaxial layer consists of a non-defect layer which is provided for device active regions. Moreover, a high density of laser-scattering centers are distributed near the interface of the epitaxial layer and the substrate wafer and the interior of the substrate, thus providing for a wafer capable of removing impurities.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: October 21, 1997
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Noriyuki Uemura, Mitsuo Kono
  • Patent number: 5665613
    Abstract: A SIMOX substrate 1 is processed through high temperature oxidation treatment after forming a mask-pattern 3 to shield specified electrodes from oxidation in order to increase partly a thickness of a buffed oxide layer 2 to form an area 4. Next, after an oxide film is removed from the surface of the substrate and LOCOS separation is practiced, MOSFET is produced by fabricating a source S and a drain D on the area 4 or the buffed oxide layer 2. Since the buried oxide layer corresponding to electrodes parts influenced by disadvantages of parasitic capacitance are thickened, an operation speed of an inverter is not much decreased and since mean thickness of the buried oxide layer can be thinner, a decrease of a drain electric current by negative electrical resistance can be suppressed. Furthermore, since the thickness of the buffed oxide layer can be controlled in response to each device, plural devices having different breakdown voltages are formed together on the same substrate.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: September 9, 1997
    Assignees: Komatsu Electronic Metals Co., Ltd., Nippon Telegraph and Telephone Corporation, NIT Electronics Technology Corporation
    Inventors: Sadao Nakashima, Katsutoshi Izumi, Norihiko Ohwada, Tatsuhiko Katayama
  • Patent number: 5658809
    Abstract: A method of producing an SOI substrate having a single-crystal silicon layer on a buried oxide layer in an electrically insulating state from the substrate by implanting oxygen ions into a single crystal silicon substrate and practicing an anneal processing in an inert gas atmosphere at high temperatures to form the buried oxide layer. After the anneal processing in which the thickness of the buried oxide layer becomes a theoretical value in conformity with the thickness of the buried oxide layer formed by the implanted oxygen, the oxidation processing of the substrate is carried out in a high temperature oxygen atmosphere.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: August 19, 1997
    Assignees: Komatsu Electronic Metals Co., Ltd., Nippon Telegraph and Telephone Corporation, NTT Electronics Technology Corporation
    Inventors: Sadao Nakashima, Katsutoshi Izumi, Norihiko Ohwada, Tatsuhiko Katayama
  • Patent number: 5537325
    Abstract: When an ingot is sliced into wafers, they are given serial numbers for identification. This makes possible to identify which any wafer being processed is of those sliced from the ingot no matter where the wafer is in a manufacturing process. Each wafer is traced so as to determine the path along which the wafer was transferred during the manufacturing process, and results are stored as wafer information.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: July 16, 1996
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Eiji Iwakiri, Shingo Fukushima, Yukitaka Takitani
  • Patent number: 5506154
    Abstract: In manufacturing a semiconductor device, when a SORI limit value of a silicon single crystal wafer to be material in manufacturing devices, and a bulk micro defect density are defined in fixed ranges for said wafer, as required by the device yield and the gettering capability, said wafer having an initial oxygen concentration capable of simultaneously satisfying said fixed ranges is subject to a preheat treatment for the formation of an oxygen precipitate nucleus by using a time capable of simultaneously satisifying a fixed range between the upper and lower limit values of said initial oxygen concentration and the fixed range of said bulk micro defect density. Use of the process of the present invention will make it possible that the SORI of a wafer is limited to its lowest extent, and a combination of a variety of conditions for insuring the BMD density required for exertion of a desired gettering capability is efficiently chosen in a short period of time without relying upon trial and error.
    Type: Grant
    Filed: July 9, 1993
    Date of Patent: April 9, 1996
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hiroyuki Kawahara, Mitsuo Kono
  • Patent number: 5488923
    Abstract: The present invention employs the construction wherein a resistor heater is disposed inside a protective cylinder whose tip is open to a molten liquid packing zone of a crucible inside a pulling apparatus so that the resistor heater is above the tip of a lower portion and temperature setting can be made so as to be capable of fusing a starting material. Since the tip of the protective cylinder is positioned inside the molten liquid at the time of pulling of a single crystal, the gaseous phase portion inside the protective cylinder and the gaseous phase portion inside the pulling apparatus are separated apart by the molten liquid and are independent of each other and a starting material polycrystal rod loaded into the protective cylinder can be supplied to the molten liquid surface inside the crucible while being molten at the lower part of the protective cylinder by the resistor heater.
    Type: Grant
    Filed: March 7, 1995
    Date of Patent: February 6, 1996
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Masato Imai, Hiroyuki Noda, Yutaka Shiraishi, Keishi Niikura, Shoei Kurosaka
  • Patent number: 5441014
    Abstract: An apparatus for pulling up a single crystal according to Czochralski method is provided with a cylindrical first screen and a second screen. The first screen is arranged in the periphery of the zone of pulling up the single crystal, said screen being constituted by a heat absorbing body at the side facing a quartz crucible and by a heat insulator at the other side and being provided with respective outward and inward annular rims at the upper and lower ends thereof, the corner of said screen facing the crucible being formed in a curved or polygonal structure, and said annular rim at the lower end being positioned in the vicinity of filling the melt in the crucible. The second screen forming a parabolic shape in the section opening at its center while enclosing the crystal pulling-up zone and being provided at its upper end with an outward annular rim.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: August 15, 1995
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Junsuke Tomioka, Kazunori Nagai, Akihiro Matsuzaki
  • Patent number: 5427056
    Abstract: The present invention employs the construction wherein a resistor heater is disposed inside a protective cylinder whose tip is open to a molten liquid packing zone of a crucible inside a pulling apparatus so that the resistor heater is above the tip of a lower portion and temperature setting can be made so as to be capable of fusing a starting material. Since the tip of the protective cylinder is positioned inside the molten liquid at the time of pulling of a single crystal, the gaseous phase portion inside the protective cylinder and the gaseous phase portion inside the pulling apparatus are separated apart by the molten liquid and are independent of each other and a starting material polycrystal rod loaded into the protective cylinder can be supplied to the molten liquid surface inside the crucible while being molten at the lower part of the protective cylinder by the resistor heater.
    Type: Grant
    Filed: April 6, 1993
    Date of Patent: June 27, 1995
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Masato Imai, Hiroyuki Noda, Yutaka Shiraishi, Keishi Niikura, Shoei Kurosaka
  • Patent number: 5385115
    Abstract: A semiconductor wafer heat treatment method for improving the yield of devices which are end products by sampling sliced single-crystal silicon wafers made by CZ method to previously calculate the thermal donor concentration of each portion on the wafers and providing them with the IG heat treatment process which causes oxygen precipitation nucleus under the heat treatment condition determined according to the thermal donor concentration so that the change value (delta Oi) of the initial oxygen concentration (initial Oi) before the IG heat treatment to the oxygen concentration after the heat treatment will be kept within a predetermined range.
    Type: Grant
    Filed: May 13, 1993
    Date of Patent: January 31, 1995
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Junsuke Tomioka, Tetsuro Akagi, Shiro Yoshino
  • Patent number: 5316742
    Abstract: A single crystal pulling apparatus using Czochralski method includes a first screen in the shape of a hollow round cylinder. One side of the first screen facing a quartz crucible is made of a heat absorbent material and another side of the first screen is made of a heat insulator material. The upper and lower ends of the first screen have an outwardly extending flange and an inwardly extending flange, respectively. The first screen surrounds a single crystal pulling zone such that its lower flange is positioned near a melt charged zone in the crucible. The apparatus also includes a second screen positioned inside the first screen. The vertical section of the second screen has the shape of a substantially parabola and the center of the bottom of the second screen is open and surrounds the single crystal pulling zone. The upper end of the second screen has an outwardly extending flange.
    Type: Grant
    Filed: October 8, 1991
    Date of Patent: May 31, 1994
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Junsuke Tomioka, Kazunori Nagai, Akihiro Matsuzaki
  • Patent number: 4857270
    Abstract: A process for manufacturing a silicon-germanium alloy comprising introducing SiH.sub.4 gas, GeCl.sub.4 gas and P-type or N-type doping gas into a reaction vessel, heating a substrate up to a temperature not lower than 750.degree. C., and depositing a thickly-grown, bulky silicon-germanium alloy upon the substrate within the reaction vessel.
    Type: Grant
    Filed: April 20, 1988
    Date of Patent: August 15, 1989
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Shinji Maruya, Yoshifumi Yatsurugi, Kazuya Togashi
  • Patent number: 4565913
    Abstract: A method for the disintegration of silicon for preparation of semiconductor materials. Polycrystalline silicon in a rod form is subjected to microwave radiation in an oven for a short period of time, whereby the rod-like polycrystalline silicon is dielectrically heated quickly from its inside thereby causing it to be disintegrated.
    Type: Grant
    Filed: July 12, 1984
    Date of Patent: January 21, 1986
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Yoshifumi Yatsurugi, Meiseki Katayama