Abstract: A method for reducing the line widths produced by patterning a semiconduc substrate with a multilayer resist mask employs a `spacer`-forming oxide layer which is non-selectively formed over the mask structure after an aperture for exposing a lower resist layer has been formed in an upper portion of the multilayer mask, but prior to etching a lower resist layer. The oxide layer is subjected to a dry systemic etch to vertically remove material of the oxide layer down to the surface of the lower resist layer. Because of the substantial step coverage of the oxide layer, a `spacer` or `stringer` portion remains along the sidewalls of the original aperture in the upper portion of the mask, whereby the dimensions of the exposure window are reduced. Retaining this sidewall spacer as an integral part of mask structure permits narrower line widths to be replicated in the underlying substrate.
Type:
Grant
Filed:
June 23, 1989
Date of Patent:
June 11, 1991
Assignee:
Korea Electronics & Telecommunications Research Institute et al.