Patents Assigned to Kovio, Inc.
  • Patent number: 8796125
    Abstract: A self-aligned top-gate thin film transistor (TFT) and a method of forming such a thin film transistor, by forming a semiconductor thin film layer; printing a doped glass pattern thereon, a gap in the doped glass pattern defining a channel region of the TFT; forming a gate electrode on or over the channel region, the gate electrode comprising a gate dielectric film and a gate conductor thereon; and diffusing a dopant from the doped glass pattern into the semiconductor thin film layer.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: August 5, 2014
    Assignee: Kovio, Inc.
    Inventors: Joerg Rockenberger, James Montague Cleeves, Arvind Kamath
  • Patent number: 8624049
    Abstract: Dopant-group substituted (cyclo)silane compounds, liquid-phase compositions containing such compounds, and methods for making the same. Such compounds (and/or ink compositions containing the same) are useful for printing or spin coating a doped silane film onto a substrate that can easily be converted into a doped amorphous or polycrystalline silicon film suitable for electronic devices. Thus, the present invention advantageously provides commercial qualities and quantities of doped semiconductor films from a doped “liquid silicon” composition.
    Type: Grant
    Filed: January 18, 2010
    Date of Patent: January 7, 2014
    Assignee: Kovio, Inc.
    Inventors: Wenzhuo Guo, Vladimir K. Dioumaev, Brent Ridley, Fabio Zürcher, Joerg Rockenberger, James Montague Cleeves
  • Patent number: 8617992
    Abstract: Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects. A metal ink may be printed for contacts as well as for local interconnects at the same time, or in the alternative, the printed metal can act as a seed for electroless deposition of other metals if different metals are desired for the contact and the interconnect lines. This approach advantageously reduces the number of processing steps and does not necessarily require any etching.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: December 31, 2013
    Assignee: Kovio, Inc.
    Inventors: Aditi Chandra, Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Mao Takashima, Erik Scher
  • Patent number: 8603426
    Abstract: A method of making hydrogenated Group IVA compounds having reduced metal-based impurities, compositions and inks including such Group IVA compounds, and methods for forming a semiconductor thin film. Thin semiconducting films prepared according to the present invention generally exhibit improved conductivity, film morphology and/or carrier mobility relative to an otherwise identical structure made by an identical process, but without the washing step. In addition, the properties of the present thin film are generally more predictable than those of films produced from similarly prepared (cyclo)silanes that have not been washed according to the present invention.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: December 10, 2013
    Assignee: Kovio, Inc.
    Inventors: Klaus Kunze, Wenzhuo Guo, Fabio Zürcher, Mao Takashima, Laila Francisco, Joerg Rockenberger, Brent Ridley
  • Patent number: 8530589
    Abstract: Embodiments relate to printing features from an ink containing a material precursor. In some embodiments, the material includes an electrically active material, such as a semiconductor, a metal, or a combination thereof. In another embodiment, the material includes a dielectric. The embodiments provide improved printing process conditions that allow for more precise control of the shape, profile and dimensions of a printed line or other feature. The composition(s) and/or method(s) improve control of pinning by increasing the viscosity and mass loading of components in the ink. An exemplary method thus includes printing an ink comprising a material precursor and a solvent in a pattern on the substrate; precipitating the precursor in the pattern to form a pinning line; substantially evaporating the solvent to form a feature of the material precursor defined by the pinning line; and converting the material precursor to the patterned material.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: September 10, 2013
    Assignee: Kovio, Inc.
    Inventors: Erik Scher, Steven Molesa, Joerg Rockenberger, Arvind Kamath, Ikuo Mori
  • Patent number: 8471308
    Abstract: Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (Vt) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the Vt of an NMOS TFT (Vtn) and the Vt of a PMOS TFT (Vtp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: June 25, 2013
    Assignee: Kovio, Inc.
    Inventors: Vivek Subramanian, Patrick Smith
  • Patent number: 8461284
    Abstract: Compositions and methods for controlled polymerization and/or oligomerization of hydrosilanes compounds including those of the general formulae SinH2n and SinH2n+2 as well as alkyl- and arylsilanes, to produce soluble silicon polymers as a precursor to silicon films having low carbon content.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: June 11, 2013
    Assignee: Kovio, Inc.
    Inventors: Dmitry Karshtedt, Joerg Rockenberger, Fabio Zürcher, Brent Ridley, Erik Scher
  • Patent number: 8460983
    Abstract: Doped semiconductor ink formulations, methods of making doped semiconductor ink formulations, methods of coating or printing thin films, methods of forming electronic devices and/or structures from the thin films, and methods for modifying and controlling the threshold voltage of a thin film transistor using the films are disclosed. A desired dopant may be added to an ink formulation comprising a Group IVA compound and a solvent, and then the ink may be printed on a substrate to form thin films and conductive structures/devices, such as thin film transistors. By adding a customized amount of the dopant to the ink prior to printing, the threshold voltage of a thin film transistor made from the doped semiconductor ink may be independently controlled upon activation of the dopant.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: June 11, 2013
    Assignee: Kovio, Inc.
    Inventors: Wenzhuo Guo, Fabio Zürcher, Arvind Kamath, Joerg Rockenberger
  • Patent number: 8461628
    Abstract: A MOS transistor with a laser-patterned metal gate, and methods for its manufacture. The method generally includes forming a layer of metal-containing material on a dielectric film, wherein the dielectric film is on an electrically functional substrate comprising an inorganic semiconductor; laser patterning a metal gate from the metal-containing material layer; and forming source and drain terminals in the inorganic semiconductor in locations adjacent to the metal gate. The transistor generally includes an electrically functional substrate; a dielectric film on at least portions of the electrically functional substrate; a laser patterned metal gate on the dielectric film; and source and drain terminals comprising a doped inorganic semiconductor layer adjacent to the metal gate. The present invention advantageously provides MOS thin film transistors having reliable electrical characteristics quickly, efficiently, and/or at a low cost by eliminating one or more conventional photolithographic steps.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: June 11, 2013
    Assignee: Kovio, Inc.
    Inventors: Criswell Choi, Joerg Rockenberger, J. Devin MacKenzie, Christopher Gudeman
  • Patent number: 8455604
    Abstract: Polysilanes, inks containing the same, and methods for their preparation are disclosed. The polysilane may have the formula H-[(AHR)n(c-AmHpm-2)q]—H, where A is independently Si or Ge; R is H, -AaHa+1Ra, halogen, aryl or substituted aryl; (n+a)?10 if q=0, q?3 if n=0, and (n+q)?6 if both n and q?0; p is 1 or 2; and m is from 3 to 12. The method may include combining a silane compound of the formula AHaR14-a, AkHgR1?h and/or c-AmHpmR1rm with a catalyst of the formula R4xR5yMXz (or an immobilized derivative thereof) to form a poly(aryl)silane; then washing the poly(aryl)silane with an aqueous washing composition and contacting the poly(aryl)silane with an adsorbent to remove the metal M. Alternatively, the method may include halogenating a polyarylsilane and reducing the halopolysilane with a metal hydride to form the polysilane.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: June 4, 2013
    Assignee: Kovio, Inc.
    Inventors: Wenzhuo Guo, Vladimir K. Dioumaev, Joerg Rockenberger, Brent Ridley
  • Patent number: 8446706
    Abstract: High precision capacitors and methods for forming the same utilizing a precise and highly conformal deposition process for depositing an insulating layer on substrates of various roughness and composition. The method generally comprises the steps of depositing a first insulating layer on a metal substrate by atomic layer deposition (ALD); (b) forming a first capacitor electrode on the first insulating layer; and (c) forming a second insulating layer on the first insulating layer and on or adjacent to the first capacitor electrode. Embodiments provide an improved deposition process that produces a highly conformal insulating layer on a wide range of substrates, and thereby, an improved capacitor.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: May 21, 2013
    Assignee: Kovio, Inc.
    Inventors: Arvind Kamath, Criswell Choi, Patrick Smith, Erik Scher, Jiang Li
  • Patent number: 8426905
    Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: April 23, 2013
    Assignee: Kovio, Inc.
    Inventors: Arvind Kamath, Erik Scher, Patrick Smith, Aditi Chandra, Steven Molesa
  • Patent number: 8424176
    Abstract: The present invention relates to methods of making and using tunable capacitors and devices. Using the methods described, one or more secondary tunable capacitors can be connected to a primary capacitor by printing a connector conducting layer or feature to obtain a desired net capacitance. Digitally printing the connector conducting layer allows the number of secondary capacitors connected into the circuit to be determined during the integrated circuit fabrication process, without the need for individual masks connecting the appropriate number of secondary capacitors. This provides an in-process or post-process trimming method to obtain the desired precision and accuracy for capacitors. Various sizes and combinations of secondary capacitors can be connected to obtain high precision capacitors and/or improved matching of capacitance values.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: April 23, 2013
    Assignee: Kovio, Inc.
    Inventors: Patrick Smith, Zhigang Wang
  • Patent number: 8397198
    Abstract: Semiconductor devices and/or structures, and methods for fabricating the same are disclosed. Embodiments of the present invention allow for production of customized products, while also minimizing production steps, avoiding some or all photolithography steps, and reducing overall production costs. Using selective deposition and patterning methods such as printing, to form metal and/or dielectric layer(s) on substrates where one or more device circuit components are pre-made in a factory, but which require further processing to obtain an electrically functional circuit, results in the ability for a user/consumer to make custom, specific and/or unique electrically functional circuits without incurring the cost and complexity of a full fabrication to form and pattern all of the layers.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: March 12, 2013
    Assignee: Kovio, Inc.
    Inventor: Jiang Li
  • Patent number: 8383952
    Abstract: Embodiments of the present invention relate to circuit layouts that are compatible with printing electronic inks, printed circuits formed by printing an electronic ink or a combination of printing and conventional blanket deposition and photolithography, and methods of forming circuits by printing electronic inks onto structures having print-compatible shapes. The layouts include features having (i) a print-compatible shape and (ii) an orientation that is either orthogonal or parallel to the orientation of every other feature in the layout.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: February 26, 2013
    Assignee: Kovio, Inc.
    Inventors: Zhigang Wang, Vivek Subramanian, Lee Cleveland
  • Patent number: 8378050
    Abstract: Methods are disclosed for making crosslinked polysilanes and polygermanes, preferably having either hydrogen or halogen substituent groups. These crosslinked polymers are prepared by catalytic polymerization such as the dehalogenative coupling or dehydrocoupling. The crosslinked polymers having no more than 10% of the chain atoms involved in crosslinking. Also disclosed are compositions containing these crosslinked polymers in a solvent to enable the composition to be deposited on a substrate using a liquid deposition technique.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: February 19, 2013
    Assignee: Kovio, Inc.
    Inventor: Vladimir K. Dioumaev
  • Patent number: 8372194
    Abstract: Methods for forming doped silane and/or semiconductor thin films, doped liquid phase silane compositions useful in such methods, and doped semiconductor thin films and structures. The composition is generally liquid at ambient temperatures and includes a Group IVA atom source and a dopant source. By irradiating a doped liquid silane during at least part of its deposition, a thin, substantially uniform doped oligomerized/polymerized silane film may be formed on a substrate. Such irradiation is believed to convert the doped silane film into a relatively high-molecular weight species with relatively high viscosity and relatively low volatility, typically by cross-linking, isomerization, oligomerization and/or polymerization. A film formed by the irradiation of doped liquid silanes can later be converted (generally by heating and annealing/recrystallization) into a doped, hydrogenated, amorphous silicon film or a doped, at least partially polycrystalline silicon film suitable for electronic devices.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: February 12, 2013
    Assignee: Kovio, Inc.
    Inventors: Fabio Zürcher, Wenzhuo Guo, Joerg Rockenberger, Vladimir K. Dioumaev, Brent Ridley, Klaus Kunze, James Montague Cleeves
  • Patent number: 8367031
    Abstract: A method of making hydrogenated Group IVA compounds having reduced metal-based impurities, compositions and inks including such Group IVA compounds, and methods for forming a semiconductor thin film. Thin semiconducting films prepared according to the present invention generally exhibit improved conductivity, film morphology and/or carrier mobility relative to an otherwise identical structure made by an identical process, but without the washing step. In addition, the properties of the present thin film are generally more predictable than those of films produced from similarly prepared (cyclo)silanes that have not been washed according to the present invention.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: February 5, 2013
    Assignee: Kovio, Inc.
    Inventors: Klaus Kunze, Wenzhuo Guo, Fabio Zurcher, Mao Takashima, Laila Francisco, Joerg Rockenberger, Brent Ridley
  • Patent number: 8350588
    Abstract: Integrated circuits and methods of permanently disabling integrated circuits are disclosed. An integrated circuit having an erasable non-volatile memory adapted to store an activation code and logic to disable the integrated circuit when the code in the erasable non-volatile memory has been altered or erased after it has been separated from a substrate, is placed into an electromagnetic field of sufficient power to erase or reprogram the erasable non-volatile memory. The entire integrated circuit is permanently disabled by erasing, altering, or reprogramming the erasable non-volatile memory. In preferred embodiments, the integrated circuit comprises a non-erasable non-volatile memory storing the activation code, and circuitry adapted to permanently disable the integrated circuit when the code in the erasable non-volatile memory does not match the activation code in the non-erasable non-volatile memory.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: January 8, 2013
    Assignee: Kovio, Inc.
    Inventor: Roger G. Stewart
  • Patent number: 8304780
    Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: November 6, 2012
    Assignee: Kovio, Inc.
    Inventors: Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Patrick Smith, Fabio Zürcher