Patents Assigned to KYOCERA SLC Technologies Corporation
  • Patent number: 9277657
    Abstract: A wiring board includes a core substrate having a number of through-holes, and buildup insulating layers and buildup wiring layers alternately laminated on upper and lower surfaces of the core substrate, in which a first through-hole group is arranged in a first region in the core board at a first arrangement density, the first region being opposed to the semiconductor element connection pad formation region, a second through-hole group is arranged in a second region at a second arrangement density lower than the first arrangement density, the second region being located in an outer peripheral portion of the core substrate and away from the first region, and a third through-hole group is arranged in a third region at a third arrangement density higher than the second arrangement density, the third region being located between the first region and the second region.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 1, 2016
    Assignee: Kyocera SLC Technologies Corporation
    Inventors: Hiroyuki Fukushima, Fumio Kumokawa
  • Publication number: 20150091760
    Abstract: The antenna board of the present invention includes: a dielectric board 11 in which a plurality of dielectric layers are laminated, a strip conductor 13, a ground conductor layer 12, a first patch conductor 14a, a second patch conductor 14b, and penetration conductors 15 and 16. The first patch conductor 14a and the second patch conductor 14b are electrically independent of each other, at least part of the second patch conductor 14b covers the position where the first patch conductor 14a is formed, and the center of the second patch conductor 14b is deviated in the extending direction of the strip conductor 13 with respect to the center of the first patch conductor 14a.
    Type: Application
    Filed: September 16, 2014
    Publication date: April 2, 2015
    Applicant: KYOCERA SLC TECHNOLOGIES CORPORATION
    Inventor: Yoshinobu SAWA
  • Publication number: 20150059170
    Abstract: There is provided a method of manufacturing a wiring board, including the steps of: preparing an insulating layer 1a including a cavity formation region X, and a separable metallic foil M formed of first and second metallic foils M1 and M2; allowing the separable metallic foil M to adhere to at least a lower face side of the insulating layer 1a with the first metallic foil M1 serving as an adhering surface; forming a cavity 2 by digging the insulating layer 1a and the separable metallic foil M in a cavity formation region X from an upper surface side of the insulating layer 1a to a depth that does not penetrate the second metallic foil M2; inserting an electronic component D into the cavity 2, and fixing the electronic component D by a fixing resin J; and peeling off the second metallic foil M2.
    Type: Application
    Filed: August 26, 2014
    Publication date: March 5, 2015
    Applicant: KYOCERA SLC TECHNOLOGIES CORPORATION
    Inventor: Daisuke NARUMI
  • Patent number: 8957321
    Abstract: A printed circuit board of the present invention includes a base body, a through-hole that penetrates through the base body in the thickness direction, and a through-hole conductor that covers an inner wall of the through-hole. The base body has a fiber layer including a plurality of glass fibers and a resin that covers the plurality of glass fibers. The glass fibers have a groove-shaped concavity on a surface exposed to the inner wall of the through-hole. The concavity is filled with a part of the through-hole conductor.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: February 17, 2015
    Assignee: KYOCERA SLC Technologies Corporation
    Inventors: Masaaki Harazono, Yoshihiro Hosoi
  • Publication number: 20150027977
    Abstract: A manufacturing method includes a step of forming a first plating mask on a base metal layer, a step of forming a main conductor layer on the base metal layer exposed from the first plating mask, a step of forming a second plating mask on them, a step of attaching a metal plating layer to an upper surface of the main conductor layer exposed from the second plating mask, a step of removing the first and second plating masks, a step of etching away a portion of the base metal layer to which the main conductor layer is not attached, and a step of forming a solder resist layer.
    Type: Application
    Filed: July 25, 2014
    Publication date: January 29, 2015
    Applicant: KYOCERA SLC Technologies Corporation
    Inventors: Kohichi OHSUMI, Sumiko NOGUCHI
  • Publication number: 20150000970
    Abstract: A wiring board includes an insulating layer having a lower layer conductor on a lower surface thereof, a plurality of semiconductor element connection pads arranged in a lattice pattern in a semiconductor element mounting portion 1a having a quadrangular shape on the insulating layer, a via hole formed in the insulating layer below each of the semiconductor element connection pads, and a via conductor filled in the via hole and formed integrally with each of the semiconductor element connection pads. The wiring board includes a reinforcing via hole formed in the insulating layer in an outer region outside an arrangement region of the semiconductor element connection pads in corner portions of the semiconductor element mounting portion, and a reinforcing via conductor formed in the reinforcing via hole.
    Type: Application
    Filed: June 27, 2014
    Publication date: January 1, 2015
    Applicant: KYOCERA SLC Technologies Corporation
    Inventors: Masakazu IINO, Teruya FUJISAKI, Takafumi OYOSHI
  • Publication number: 20150000965
    Abstract: A wiring board 10a according to the present invention is provided with an insulating board 1 laminated at least one insulating layer 1b having a via hole 8 on at least one surface of a core layer 1a, a via conductor 2b formed inside the via hole 8 and containing a low resistance material, and a connection pad formed at the surface of the insulating layer 1b and including a thin film resistor layer 3a containing a high resistance material, wherein the thin film resistor layer 3a is adhered to the insulating layer 1b in such a manner as to cover the via conductor 2b and the insulating layer 1b surrounding the via conductor 2b.
    Type: Application
    Filed: June 27, 2014
    Publication date: January 1, 2015
    Applicant: KYOCERA SLC TECHNOLOGIES CORPORATION
    Inventor: Makoto SHIROSHITA
  • Publication number: 20150000968
    Abstract: In a wiring board, on an insulating layer of an outermost layer, there are provided a plurality of strip-shaped wiring conductors which are partially provided with semiconductor element connection pads to which electrode terminals of a semiconductor element are connected, at positions which prevent the semiconductor element connection pads adjacent to each other from being laterally arranged, and a solder resist layer having openings for individually exposing the semiconductor element connection pads is adhered on the insulating board as the outermost layer and on the strip-shaped wiring conductors, wherein the solder resist layer internally contains an insulating filler, and the insulating filler is sunk below the upper surfaces of the strip-shaped wiring conductors.
    Type: Application
    Filed: June 23, 2014
    Publication date: January 1, 2015
    Applicant: KYOCERA SLC Technologies Corporation
    Inventors: Hirofumi ISHIBASHI, Masanori TADA
  • Publication number: 20140353021
    Abstract: A wiring board 10 includes a lower wiring conductor 1, an upper insulating layer 2 laminated on the lower wiring conductor 1 and having a via hole 5 where a bottom surface is the lower wiring conductor 1, and a via conductor 3 connected to the lower wiring conductor 1 and filling the via hole 5; and the upper insulating layer 2 includes a first resin layer 2a and a second resin layer 2b sequentially laminated on the lower wiring conductor 1, the via hole 5 has an annular groove 5a over a whole circumference of the inner wall in a boundary between both resin layers 2a and 2b, and the via conductor 3 fills the groove 5.
    Type: Application
    Filed: May 23, 2014
    Publication date: December 4, 2014
    Applicant: KYOCERA SLC TECHNOLOGIES CORPORATION
    Inventor: Hidetoshi YUGAWA
  • Publication number: 20140353026
    Abstract: A wiring board according to the present invention includes an insulating layer 3, a semiconductor element mounting portion 1a, semiconductor element connection pads 11, via holes 8, and via conductors 10. The semiconductor element connection pads 11 aligned on the semiconductor element mounting portion 1a include first semiconductor element connection pads 11a and other second semiconductor element connection pads 11b, and the diameters of the via conductors 10 connected to the first semiconductor element connection pads 11a are larger than the diameters of the via conductors 10 connected to the second semiconductor element connection pads 11b.
    Type: Application
    Filed: May 30, 2014
    Publication date: December 4, 2014
    Applicant: KYOCERA SLC TECHNOLOGIES CORPORATION
    Inventor: Seiji HATTORI
  • Patent number: 8890001
    Abstract: A wiring board of the present invention includes a substrate including a woven fabric formed of a plurality of glass fibers and a resin covering the woven fabric; a plurality of through holes T penetrating through the substrate in a thickness direction thereof; and a plurality of through hole conductors adhered to inner walls of the through holes T respectively. The through holes T include a first through hole and a second through hole, and, in the woven fabric, the number of the glass fibers through which the first through hole penetrates is larger than the number of the glass fibers through which the second through hole penetrates. In the first and second through holes, portions thereof having narrowest widths are surrounded by the woven fabric, and the narrow width portion of the first through hole is smaller than the narrow width portion of the second through hole.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: November 18, 2014
    Assignee: Kyocera SLC Technologies Corporation
    Inventors: Takayuki Nejime, Masaaki Harazono, Yoshihiro Hosoi
  • Publication number: 20140318834
    Abstract: A wiring board of the present invention includes a core substrate in which wiring conductors are formed on both surfaces of an insulating plate, and a build-up layer in which a conductor layer is formed on a surface of an insulating resin layer having a higher coefficient of thermal expansion than that of the insulating plate. At least one build-up layer is stacked on one surface or both surfaces of the core substrate. Both surfaces of the insulating plate have different coefficients of thermal expansion. At least one build-up layer is stacked on a surface having a lower coefficient of thermal expansion. No build-up layer is stacked on the opposite surface, or a smaller number of build-up layers than that of the build-up layer formed on the surface having the lower coefficient of thermal expansion is formed on the opposite surface.
    Type: Application
    Filed: May 6, 2014
    Publication date: October 30, 2014
    Applicant: KYOCERA SLC Technologies Corporation
    Inventor: Tomoharu TSUCHIDA
  • Publication number: 20140291005
    Abstract: A wiring board includes a core substrate having a number of through-holes, and buildup insulating layers and buildup wiring layers alternately laminated on upper and lower surfaces of the core substrate, in which a first through-hole group is arranged in a first region in the core board at a first arrangement density, the first region being opposed to the semiconductor element connection pad formation region, a second through-hole group is arranged in a second region at a second arrangement density lower than the first arrangement density, the second region being located in an outer peripheral portion of the core substrate and away from the first region, and a third through-hole group is arranged in a third region at a third arrangement density higher than the second arrangement density, the third region being located between the first region and the second region.
    Type: Application
    Filed: March 21, 2014
    Publication date: October 2, 2014
    Applicant: KYOCERA SLC TECHNOLOGIES CORPORATION
    Inventors: Hiroyuki FUKUSHIMA, Fumio KUMOKAWA
  • Patent number: 8836361
    Abstract: A wiring board and a probe card using the wiring board which respond to a demand for improving electrical reliability.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: September 16, 2014
    Assignee: KYOCERA SLC Technologies Corporation
    Inventors: Takayuki Taguchi, Kenji Terada
  • Publication number: 20140209361
    Abstract: A wiring board according to the present invention has an insulating board 1 including a land conductor layer 14 on a surface thereof; an insulating layer 5 formed on the insulating board 1; a via hole 6 extending from an upper surface of the insulating layer 5 to the land conductor layer 14; a via conductor 7 formed in the via hole 6 and formed of a plated metal layer; and a wiring conductor 3b formed on the via conductor 7 and electrically connected to the via conductor 7, wherein the via hole 6 is provided with a protruding portion 8a formed of copper foil and protruding from a periphery of an opening of the via hole 6 toward a center of the opening.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 31, 2014
    Applicant: KYOCERA SLC Technologies Corporation
    Inventors: Makoto NAKAI, Takashi KATO
  • Publication number: 20140182126
    Abstract: A method for manufacturing a wiring board according to the present invention includes the steps of preparing a supporting substrate having a product forming region and a marginal region; preparing a separable metal foil whose area is larger than that of the product forming region and is smaller than that of the supporting substrate; fixing the separable metal foil to the supporting substrate by burying into the supporting substrate; forming a build-up section on the buried separable metal foil; integrally cutting out the supporting substrate, the separable metal foil and the build-up section; obtaining a laminated body for wiring board composed of the second metal foil and the build-up section by separating the first metal foil and the second metal foil; and forming the wiring conductor layer by removing a part of the second metal foil.
    Type: Application
    Filed: December 10, 2013
    Publication date: July 3, 2014
    Applicant: KYOCERA SLC Technologies Corporation
    Inventors: Daisuke NARUMI, Yoshinori NAKATOMI, Masaharu YASUDA
  • Publication number: 20140116762
    Abstract: A wiring board includes a rectangular mount region surrounded by four sides circumscribed to pads located in an outer peripheral area among a plurality of pads arranged in a substantially matrix form, a corner pad close to a corner of the mount region, and a second via-conductor and a second corner via-conductor electrically connected to the corner pad via a first via-conductor and a first wiring conductor. In the wiring board, a distance in a plane direction between the second corner via-conductor and a center of the mount region is smaller than a distance in the plane direction between the corner pad and the center of the mount region.
    Type: Application
    Filed: October 22, 2013
    Publication date: May 1, 2014
    Applicant: KYOCERA SLC Technologies Corporation
    Inventor: Takafumi OYOSHI
  • Patent number: 8698007
    Abstract: There is provided a printed circuit board including an insulating substrate having a guide hole, a solder resist layer coated on a surface of the insulating substrate, and a connection pad arranged on the surface of the insulating substrate and having an outer periphery covered with the solder resist layer and a central portion exposed in an opening formed in the solder resist layer. The solder resist layer has a positioning hole having a diameter smaller than that of the guide hole and formed by photolithography above the guide hole simultaneously with the opening.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: April 15, 2014
    Assignee: Kyocera SLC Technologies Corporation
    Inventor: Keizou Sakurai
  • Publication number: 20140092569
    Abstract: A wiring board includes a base wiring board 10 and a frame wiring board 20. The base wiring board 10 has an element mounting portion 1a and a frame-shaped frame joining portion 1b on the upper surface and a solder resist layer 4 deposited in a portion between the element mounting portion 1a and the frame joining portion 1b. In the wiring board 10, a first joining pad 6 provided in the frame joining portion 1b and a second joining pad 16 provided in a lower surface of the frame wiring board 20 are joined together via a solder bump H so that a gap may be formed between the frame joining portion 1b and the frame wiring board 20. The base wiring board 10 has a resin injection hole 8 penetrating through the base wiring board 10 in the frame joining portion 1b, and the gap is filled with a sealing resin 18.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 3, 2014
    Applicant: KYOCERA SLC Technologies Corporation
    Inventor: Keizou SAKURAI
  • Publication number: 20140048323
    Abstract: A wiring board including an insulating board formed such that an inner insulating layer is laminated under a front insulating layer, a pair of semiconductor element connection pads for a signal, formed on the front insulating layer, and a pair of strip-shaped wiring conductors formed on the inner insulating layer, having connection ends connected to the pair of pads for the signal under the pair of pads through via holes, and having parallel extending portions extending to an outer peripheral portion from the connection ends on the inner insulating layer in parallel to each other, where a part from the connection end to one part of the parallel extending portion has a width smaller than a width of a residual part, and length equal to or less than one-sixteenth of a wavelength of a signal transmitting in the pair of strip-shaped wiring conductors.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 20, 2014
    Applicant: KYOCERA SLC Technologies Corporation
    Inventor: Hisayoshi WADA