Patents Assigned to Kyoei Sangyo Co., Ltd.
  • Patent number: 6794680
    Abstract: In a semiconductor device having a pad, a first conductor and a second conductor are arranged at a surface of the pad. The first conductor has hardness that is greater than that of the second conductor and not less than that of a probe stylus. The first conductor is arranged at the surface of the pad such that the probe stylus hits or rubs against the first conductor at least one time while the probe stylus is in contact with and sliding on the surface of the pad.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: September 21, 2004
    Assignees: Renesas Technology Corp., Kyoei Sangyo Co., Ltd.
    Inventors: Naoki Kimura, Keiji Sugihara
  • Publication number: 20040140467
    Abstract: In a semiconductor device having a pad, a first conductor and a second conductor are arranged at a surface of the pad. The first conductor has hardness that is greater than that of the second conductor and not less than that of a probe stylus. The first conductor is arranged at the surface of the pad such that the probe stylus hits or rubs against the first conductor at least one time while the probe stylus is in contact with and sliding on the surface of the pad.
    Type: Application
    Filed: July 3, 2003
    Publication date: July 22, 2004
    Applicants: RENESAS TECHNOLOGY CORP., KYOEI SANGYO CO., LTD.
    Inventors: Naoki Kimura, Keiji Sugihara
  • Publication number: 20040120085
    Abstract: A semiconductor device with a surge protection circuit includes a surge protection circuit electrically connected to a signal input terminal and having an npn transistor and an npn transistor. The semiconductor device is configured such that the npn transistor is more susceptible to breakdown than the npn transistor, by implementing such a configuration that a narrowest region of a base of the npn transistor has a width different from that of a narrowest region of a base of the npn transistor. Thus, a semiconductor device with a surge protection circuit attaining a normal operation can be obtained.
    Type: Application
    Filed: August 18, 2003
    Publication date: June 24, 2004
    Applicants: RENESAS TECHNOLOGY CORP., KYOEI SANGYO CO., LTD.
    Inventors: Fumitoshi Yamamoto, Yasufumi Murai, Keiichi Furuya
  • Patent number: 6633345
    Abstract: A receiver includes a tuner that converts an FM radio broadcast signal into an intermediate frequency signal that has the same frequency as a sound intermediate frequency subcarrier signal when receiving the television broadcast signal and outputs the intermediate frequency signal when receiving the FM radio broadcast signal, a SAW filter passing only an intermediate frequency band of the output of the tuner, a video detector detecting a video signal containing a sound subcarrier signal when receiving the television broadcast signal and detecting a sound subcarrier signal when receiving the FM radio broadcast signal, a VIFAGC circuit making the video signal have a constant amplitude, and an AGC circuit making a sound subcarrier signal output from a band pass filter have a constant amplitude.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: October 14, 2003
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Kyoei Sangyo Co., Ltd.
    Inventors: Hiroshi Izuta, Akio Ohnishi
  • Patent number: 5936288
    Abstract: Anode and cathode regions at a principal surface of a semiconductor substrate have the same characteristics as source and drain regions of a P type MOS transistor. A cathode region is superposed partially on the anode region at the principal surface of the semiconductor substrate, the cathode region having the same characteristics as source and drain regions of an N type MOS transistor. The cathode and anode regions form a Zener diode. The Zener diode may be short-circuited by a large current flow, i.e., zapping, or used as a voltage regulator.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: August 10, 1999
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Kyoei Sangyo Co. Ltd.
    Inventors: Kazuhito Tsuchida, Kouji Kashimoto, Satoshi Kadono
  • Patent number: 5425011
    Abstract: In response to a test signal received at a test terminal, one terminal of a first computation circuit and three terminals of a second computation circuit are each provided with a reference voltage, or a ground potential, which is available at reference voltage supply terminals associated with photo detectors. Another terminal of the first computation circuit and the second computation circuit are each provided with a detected voltage. If the functions of the computation circuits are not defective, function signals will be obtained each having a value which corresponds to an imbalance between the detected voltage and the reference voltage. Thus, only one test terminal is required, which reduces the size of the semiconductor integrated circuit.
    Type: Grant
    Filed: October 12, 1993
    Date of Patent: June 13, 1995
    Assignees: Kyoei Sangyo Co., Ltd., Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Kusano, Seiji Takahara