Abstract: A control signal may be produced in response to an assertion of a switch signal by asserting the control signal, waiting an adaptive delay after the assertion of the switch signal, de-asserting the control signal in response to the expiration of the adaptive delay, and re-asserting the control signal in response to a current generated according to the control signal becoming zero. The adaptive delay may be adjusted according to a voltage generated using the current. A circuit may include an XOR gate producing the control signal from a switch signal and an output of a Set-Reset Flip-Flop (SRFF), a zero-detect circuit that resets the SRFF when a current generated using the control circuit becomes zero, and a delay circuit to set the SRFF an adaptive delay after assertion of the switch signal and to adjust the adaptive delay according to a voltage generated by the current.