Abstract: An output node at a plus side of a diode bridge (DB2) is connected to a drain of a transistor (Q1), and a source of the transistor (Q1) is connected to an output node at a minus side the diode bridge (DB2). One end of a resister (R1) is connected to the drain of the transistor (Q1), and the other end of the resister (R1) is connected to a gate of the transistor (Q1). One end of a resister (R2) is connected to the gate of the transistor (Q1), and the other end of the resister (R2) is connected to the source of the transistor (Q1). A capacitor (C1) is connected in parallel to the resister (R2).
Type:
Grant
Filed:
October 19, 2006
Date of Patent:
February 21, 2012
Assignees:
NTT Advanced Technology Corporation, Nippon Telegraph and Telephone Corporation, Kyoshin Electric Works, Ltd.