Abstract: The present invention discloses a semiconductor memory device. The device comprises memory cells for storing data, bit line pairs connected to the memory cells and for transmitting the data, data line pairs for transmitting the data to the bit line pairs, column select transistors for controlling transmission of the data between the bit line pairs and the data line pairs, precharging transistors for precharging the data line pairs, an address state transition detecting means for generating an address state transition detection pulse by detecting state transition of an address signal, a data state transition detection means for generating a data state transition detection pulse by detecting state of the data, a control circuit for enabling the precharging transistors in response to the address state transition detection pulse, the data state transition detection pulse, and a write enable signal, thereby protecting an entry of invalid data by ensuring enough write recovery time and data hold time.