Patents Assigned to Kyushu Fujitsu Electronics Limited
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Patent number: 6379997Abstract: A semiconductor device includes a semiconductor element, a holding substrate holding the semiconductor element, a frame body provided on the holding substrate so as to surround the semiconductor element and having a hole which communicates to a space formed between the holding substrate and the frame body and the frame body and the holding substrate form a housing, a plurality of leads having inner lead portions connected to the semiconductor element and outer lead portions extending outside the frame body, and a resin filling the space and encapsulating the semiconductor element and the inner lead portions. All of the outer lead portions extend outside the housing from one side of the housing.Type: GrantFiled: June 13, 2000Date of Patent: April 30, 2002Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Toshimi Kawahara, Sinya Nakaseko, Mitsunada Osawa, Mayumi Osumi, Hiroyuki Ishiquro, Yoshitugu Katoh, Junichi Kasai, Shinichirou Taniguchi, Yuji Sakurai
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Patent number: 6111306Abstract: A semiconductor device includes a semiconductor element, a holding substrate holding the semiconductor element, a frame body provided on the holding substrate so as to surround the semiconductor element and having a hole which communicates to a space formed between the holding substrate and the frame body and the frame body and the holding substrate form a housing, a plurality of leads having inner lead portions connected to the semiconductor element and outer lead portions extending outside the frame body, and a resin filling the space and encapsulating the semiconductor element and the inner lead portions. All of the outer lead portions extend outside the housing from one side of the housing.Type: GrantFiled: October 6, 1997Date of Patent: August 29, 2000Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Toshimi Kawahara, Sinya Nakaseko, Mitsunada Osawa, Mayumi Osumi, Hiroyuki Ishiguro, Yoshitugu Katoh, Junichi Kasai, Shinichirou Taniguchi, Yuji Sakurai
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Patent number: 6034428Abstract: A semiconductor device includes a semiconductor chip, and a multi-layered member connected to the semiconductor chip. The multi-layered member includes one or a plurality of wiring layers and one or a plurality of insulating layers alternately stacked. The one or the plurality of insulating layers have holes. The multi-layered member has electrode parts which include deformed portions of the above one or the plurality of wiring layers obtained by deforming the above one or the plurality of wiring layers via said holes.Type: GrantFiled: November 8, 1996Date of Patent: March 7, 2000Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Toshimi Kawahara, Hiroyuki Ishiguro, Mitsunada Osawa, Shinichirou Taniguchi, Mayumi Osumi, Shinya Nakaseko, Yoshitugu Katoh, Junichi Kasai
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Patent number: 5976618Abstract: A process capable of forming an inorganic film which can be used at a relatively large thickness equivalent to, or greater than, the thickness of an organic SOG, without being subjected to oxidation by O.sub.2 plasma treatment used in a fabrication process of a semiconductor device. Polysilazane is first coated on a base, and the resulting polysilazane film is converted to a silicon dioxide film.Type: GrantFiled: September 29, 1997Date of Patent: November 2, 1999Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Shun-ichi Fukuyama, Daitei Shin, Yuki Komatsu, Hideki Harada
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Patent number: 5821613Abstract: A method of manufacturing a semiconductor device which includes a semiconductor chip and a plastic package of a thermosetting polymer encapsulating the semiconductor chip through a molding process. The thermosetting polymer of the plastic package fully or partially covers a bottom surface of the semiconductor chip. An ultraviolet cleaning process is performed for cleaning the bottom surface of the semiconductor chip prior to the molding process.Type: GrantFiled: August 28, 1997Date of Patent: October 13, 1998Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Akira Takashima, Mitsutaka Sato, Shinichirou Taniguchi
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Patent number: 5804467Abstract: A semiconductor device includes a substrate having top and bottom surfaces, a semiconductor element mounted on the top surface of the substrate, and a resin package made of a resin and encapsulating the semiconductor element. The substrate includes at least one resin gate hole enabling the resin to be introduced from the bottom surface of the substrate via the resin gate hole when encapsulating the semiconductor element by the resin.Type: GrantFiled: May 13, 1997Date of Patent: September 8, 1998Assignees: Fujistsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Toshimi Kawahara, Shinya Nakaseko, Mitsunada Osawa, Shinichirou Taniguchi, Mayumi Osumi, Hiroyuki Ishiguro, Yoshitugu Katoh, Junichi Kasai
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Patent number: 5804468Abstract: A process for manufacturing semiconductor device having a package in which a semiconductor device is sealed includes a base, and a metallic film is formed on a surface of the base. The semiconductor chip is formed on the metallic film. A pad formed on the semiconductor chip is connected to the metallic film by a wire. A sealing layer is formed on the metallic film. Leads are formed on the glass layer. A connecting layer is formed on the metallic film and contains electrically conductive particles. The connecting layer is in contact with a lead for a power supply system and connecting the metallic film to the lead.Type: GrantFiled: November 21, 1995Date of Patent: September 8, 1998Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Michio Sono, Ichiro Yamaguchi, Toshio Hamano, Yoshihiro Kubota, Michio Hayakawa, Yoshihiko Ikemoto, Yukio Saigo, Naomi Miyaji
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Patent number: 5783459Abstract: A metal wiring is fabricated for a semiconductor device by fabricating an metal layer made of, a aluminum alloy on a semiconductor substrate through an insulation layer and an undercoating layer for the metal layer, optically patterning a resist layer for producing a resist pattern, radiating ultraviolet rays onto the resist pattern for curing the resist pattern so that the resist pattern becomes a cured resist pattern, etching the metal layer with reactive gas including chlorine by using the cured resist pattern as a mask so as to produce a metal wiring under the cured resist pattern and ashing the cured resist pattern by down flow ashing of oxygen gas including hydrogen and/or hydrogen monoxide, producing the metal wiring to the semiconductor device, wherein the curing by radiation with ultraviolet rays reduces the amount of decomposed polymer on the pattern resist, and therefore on the metal wiring, which would otherwise have formed as a result of this down flow ashing with oxygen.Type: GrantFiled: February 9, 1994Date of Patent: July 21, 1998Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Tamotsu Suzuki, Kouichi Kawahara
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Patent number: 5770260Abstract: A process capable of forming an inorganic film which can be used at a relatively large thickness equivalent to, or greater than, the thickness of an organic SOG, without being subjected to oxidation by O.sub.2 plasma treatment used in a fabrication process of a semiconductor device. Polysilazane is first coated on a base, and the resulting polysilazane film is converted to a silicon dioxide film.Type: GrantFiled: June 30, 1997Date of Patent: June 23, 1998Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Shun-ichi Fukuyama, Daitei Shin, Yuki Komatsu, Hideki Harada, Yoshihiro Nakata, Michiko Kobayashi, Yoshiyuki Okura
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Patent number: 5750421Abstract: A semiconductor device including a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.Type: GrantFiled: January 27, 1997Date of Patent: May 12, 1998Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited, Fujitsu Automation LimitedInventors: Junichi Kasai, Kazuto Tsuji, Norio Taniguchi, Takashi Mashiko, Masao Sakuma, Yukio Saigo, Yoshiyuki Yoneda, Masashi Takenaka
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Patent number: 5736428Abstract: A process for manufacturing semiconductor device including a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.Type: GrantFiled: January 27, 1997Date of Patent: April 7, 1998Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited, Fujitsu Automation LimitedInventors: Junichi Kasai, Kazuto Tsuji, Norio Taniguchi, Takashi Mashiko, Masao Sakuma, Yukio Saigo, Yoshiyuki Yoneda, Masashi Takenaka
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Patent number: 5731720Abstract: A semiconductor integrated circuit device is intended to prevent generation of an unnecessary leak current and hence to reduce power consumption.Type: GrantFiled: January 21, 1997Date of Patent: March 24, 1998Assignees: Fujitsu Limited, Fujitsu VLSI Limited, Kyushu Fujitsu Electronics LimitedInventors: Takaaki Suzuki, Makoto Niimi, Hideaki Kawai, Masato Kaida
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Patent number: 5724233Abstract: A chip-on chip type semiconductor device is provided in which semiconductor chips provided in a package cannot be displaced during a transfer molding process so as to eliminate a short circuit. At least two lead frames are provided in and extend from the package so that the first semiconductor chip and the second semiconductor chip can be electrically connected to external devices. A die stage is provided between the first semiconductor chip and the second semiconductor chip. A bonding wire is provided for wiring between the first semiconductor chip and the lead frames, and TAB leads connect the second semiconductor chip to the lead frames. The lead frames may extend between the first and second semiconductor devices instead of the die stage. The lead frames may include one having a portion extending in a direction perpendicular to the longitudinal direction of the lead frames between the first and second semiconductor chips.Type: GrantFiled: May 15, 1996Date of Patent: March 3, 1998Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Tosiyuki Honda, Takao Haranosono
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Patent number: 5680064Abstract: A first level converter is provided with an input transistor circuit and an output transistor circuit. The input transistor circuit is supplied with power from a first power source and outputs a complementary signal on the basis of an input signal. The output transistor circuit is supplied with power from a second power source, and amplifies and outputs the complementary signal. A second level converter is provided with a pulse generating circuit and a signal output circuit. The pulse generating circuit is supplied with power from the first driving power source, and generates a one-shot pulse signal. The signal output circuit is supplied with power from the second driving power source, latches the one-shot pulse signal and outputs the signal. The semiconductor integrated circuit is provided with a first circuit system, a level conversion circuit and a second circuit system. The first circuit system is driven by being supplied with power from the first driving power source.Type: GrantFiled: May 28, 1996Date of Patent: October 21, 1997Assignees: Fujitsu Limited, Fujitsu VLSI Limited, Kyushu Fujitsu Electronics LimitedInventors: Satoru Masaki, Akinori Yamamoto, Fusao Seki, Fumitaka Asami, Kazuo Ohno, Masao Imai, Shinya Udo
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Patent number: 5679978Abstract: A semiconductor device includes a substrate having top and bottom surfaces, a semiconductor element mounted on the top surface of the substrate, and a resin package made of a resin and encapsulating the semiconductor element. The substrate includes at least one resin gate hole enabling the resin to be introduced from the bottom surface of the substrate via the resin gate hole when encapsulating the semiconductor element by the resin.Type: GrantFiled: October 24, 1994Date of Patent: October 21, 1997Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Toshimi Kawahara, Shinya Nakaseko, Mitsunada Osawa, Shinichirou Taniguchi, Mayumi Osumi, Hiroyuki Ishiguro, Yoshitugu Katoh, Junichi Kasai
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Patent number: 5637923Abstract: A semiconductor device including a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.Type: GrantFiled: May 31, 1995Date of Patent: June 10, 1997Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited, Fujitsu Automation LimitedInventors: Junichi Kasai, Kazuto Tsuji, Norio Taniguchi, Takashi Mashiko, Masao Sakuma
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Patent number: 5579208Abstract: A chip-on chip type semiconductor device is provided in which semiconductor chips provided in a package cannot be displaced during a transfer molding process so as to eliminate a short circuit. At least two lead frames are provided in and extend from the package so that the first semiconductor chip and the second semiconductor chip can be electrically connected to external devices. A die stage is provided between the first semiconductor chip and the second semiconductor chip. A bonding wire is provided for wiring between the first semiconductor chip and the lead frames, and TAB leads connect the second semiconductor chip to the lead frames. The lead frames may extend between the first and second semiconductor devices instead of the die stage. The lead frames may include one having a portion extending in a direction perpendicular to the longitudinal direction of the lead frames between the first and second semiconductor chips.Type: GrantFiled: June 2, 1995Date of Patent: November 26, 1996Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Tosiyuki Honda, Takao Haranosono
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Patent number: 5497114Abstract: A flip-flop circuit includes a first switch for controlling passing of input data in response to a single clock signal, a first inverter for inverting the data passed through the first switch, a second inverter for inverting the data output from the first inverter into inverted data and for inputting the inverted data to the first inverter, a second switch for controlling passing of the data output from the first inverter in response to the single clock signal, a third inverter for inverting the data passed through the second switch, and a fourth inverter for inverting the data output from the third inverter into inverted data and for inputting the inverted data to the third inverter, where the first inverter has a driving capability larger than that of the second inverter, and the third inverter has a driving capability larger than that of the fourth inverter.Type: GrantFiled: September 2, 1994Date of Patent: March 5, 1996Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Motoki Shimozono, Shinya Udo, Fumitaka Asami
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Patent number: 5497032Abstract: A semiconductor device having a package in which a semiconductor device is sealed includes a base, and a metallic film is formed on a surface of the base. The semiconductor chip is formed on the metallic film. A pad formed on the semiconductor chip is connected to the metallic film by a wire. A sealing layer is formed on the metallic film. Leads are formed on the glass layer. A connecting layer is formed on the metallic film and contains electrically conductive particles. The connecting layer is in contact with a lead for a power supply system and connecting the metallic film to the lead.Type: GrantFiled: March 16, 1994Date of Patent: March 5, 1996Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Michio Sono, Ichiro Yamaguchi, Toshio Hamano, Yoshihiro Kubota, Michio Hayakawa, Yoshihiko Ikemoto, Yukio Saigo, Naomi Miyaji
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Patent number: 5479051Abstract: A semiconductor device includes at least a first semiconductor chip and a second semiconductor chip each having a first surface and a second surface. The second surface of the first semiconductor chip confronts the first surface of the second semiconductor chip. Additionally, the semiconductor device includes a plurality of leads having inner portions and outer portions, where the inner portions of the leads are electrically coupled to selected portions on one of the first and second surfaces of each of the first and second semiconductor chips. An insulator is interposed between the second surface of the first semiconductor chip and the first surface of the second semiconductor chip at portions other than the selected portions. Further, a resin package encapsulates the first and second semiconductor chips so that the outer portions of the leads project outside the resin package.Type: GrantFiled: September 24, 1993Date of Patent: December 26, 1995Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Masaki Waki, Tosiyuki Honda, Yukio Gomi