Abstract: A semiconductor device includes a semiconductor chip having top and bottom surfaces, upper leads electrically coupled to the semiconductor chip, where a first gap is formed between the upper leads and the top surface of the semiconductor chip, lower leads electrically coupled to the semiconductor chip, where a second gap is formed between the lower leads and the bottom surface of the semiconductor chip, and an encapsulating resin which encapsulates the semiconductor chip so as to maintain the first and second gaps.

Abstract: The present invention relates to an output circuit and a semiconductor integrated circuit. It is an object of the present invention to cut off a passage of a current through a forward parasitic diode of a transistor connected to a power supply line and a ground line at a time of suspension of output operation of the relevant circuit, and to raise an output high level to the utmost and lower an output low level to the utmost at time of normal output operation.

Abstract: A process for manufacturing semiconductor device including a semiconductor chip having top and bottom surfaces, upper leads electrically coupled to the semiconductor chip, where a first gap is formed between the upper leads and the top surface of the semiconductor chip, lower leads electrically coupled to the semiconductor chip, where a second gap is formed between the lower leads and the bottom surface of the semiconductor chip, and an encapsulating resin which encapsulates the semiconductor chip so as to maintain the first and second gaps.

Abstract: A lead frame body having a chip mounting surface comprises first, second and third successive, laminated layers each having lower and upper surface, the lower main surface of the first layer defining a bottom main surface of the lead frame body and the upper main surface of the third layer defining the chip-mounting surface of the lead frame body. The first, second and third layers are formed of respective, different materials, the material of the second layer having a higher etching rate than the respective etching rate of the materials of the first and third layers. A plurality of spaced openings are formed in the first layer and which respectively correspond to and are in communication with a corresponding plurality of spaced hollow cavities in the second layer.