Abstract: Provided are a generation device and the like for generating a new vector whose volume can be reduced rapidly when an output pattern derived from a decompressor of a logic circuit under test includes an unspecified bit in relation to the logic circuit under test. The output pattern includes unspecified bits. In step SS1, classification unit classifies the unspecified bits and determines if an unspecified bit is an implied bit or not. The implied bit is an unspecified bit if its value is a logic value determined as logic value 0 or 1 relating to logic bits in the initial vector and according to a predetermined condition (such as compressibility) among bits in the initial vector derived from the upstream logic circuit 1. In step SS1, the unspecified bits which are not implied bits are classified as free bits. The classification unit classifies free bit sets in step SS2, and further classifies free bits to identify compatible free bit sets.