Abstract: In one embodiment, the digital pulse width modulator of these teachings includes comparators and a number of phases and capable of increasing resolution without increasing clock frequency. In another embodiment, the digital pulse width modulator (DPWM) of these teachings includes equality comparators and a number of phases and increases resolution without increasing clock frequency. A further embodiment of the system of these teachings includes a priority encoded comparator component (in one instance including a number of comparators) comparing duty cycle commands against preset minimums, that embodiment being referred to as a frequency Foldback component. Other embodiments and embodiments of the method of these teachings are also disclosed.

Abstract: Methods and systems for digital control utilizing oversampling.

Abstract: A controller for switching power supplies includes a nonlinear controller component capable of providing a duty cycle to a pulse width modulator. The duty cycle corresponds to at least one predetermining switching power supply state variable. A nonlinear controller component receives as inputs at least one predetermined switching power supply state variable. A relationship between duty cycle and at least one predetermined switching power supply state variable is obtained by a predetermined method. The nonlinear controller component comprises memory for access by an application component. The memory includes a data structure stored in memory and a plurality of duty cycles. Each of the plurality of duty cycles has a corresponding at least one predetermined switching power supply state variable. Each duty cycle, when provided to the pulse width modulator of the switching power supply, provides a predetermined switching power supply output.

Abstract: A system includes a first switch connected to a voltage input and a switching node. A second switch is connected to the switching node and a reference potential. A first circuit generates first rising edges and first falling edges by comparing a voltage at the switching node to a first voltage reference. The first voltage reference is between the reference potential and the voltage input. A second circuit generates second rising edges and second falling edges by comparing the switching node voltage to a second voltage reference. The second voltage reference is less than the reference potential. The controller calculates delay times based on the first rising edges, the first falling edges, the second rising edges and the second falling edges. The controller generates drive signals for the first switch and the second switch based on a duty cycle and the delay times.

Abstract: A nonlinear PWM controller for switching power supplies.

Abstract: Systems and methods control timing of switches in power regulators and power amplifiers. The systems and methods monitor a switch node voltage and obtain rising and falling edges of signals obtained from the monitoring. The systems and methods utilize the rising and falling edges of switch drive signals and predetermined data to obtain delay times for subsequent drive signals.

Abstract: A method and apparatus for converting a DC voltage to a lower DC voltage, provides for conducting current from an input terminal, through an inductor to charge a capacitor connected to the inductor at an output terminal and to provide a varying range of load current from the output terminal, alternately switching the input terminal between a supply voltage and a ground potential to produce a desired voltage at the output terminal that is lower than the supply voltage, while providing the varying range of load current, and disconnecting the input terminal from both the supply voltage and the ground potential to reduce an increase in voltage at the output terminal caused by a substantial reduction in the load current, while current through the inductor adjusts in response to the reduced load current.

Abstract: Feedforward compensated systems and methods for their use in disturbance rejection in switching power converters and other systems. In one instance, a compensating component receives a sensed output and provides a duty cycle adjustment signal, the duty cycle adjustment signal being obtained from signals indicative of present and past load current variations. In another instance, an adaptive compensating component receives a sensed output and provides an adjustment signal for compensating for load variations. A compensator design component receives the digitized sensed output and of provides compensating component parameters to the adaptive compensating component; the compensator design component including a learning function.

Abstract: Methods and systems for digital control utilizing oversampling.

Abstract: Methods and systems for digital control.