Abstract: A system for determining the median of a plurality of data values comprises a plurality of field programmable gate arrays (FPGA), a plurality of inter FPGA links, an input router, a plurality of median modules, and a plurality of output transfer modules. Each FPGA includes a plurality of configurable logic elements and configurable storage elements from which the other components are formed. The inter FPGA link allows communication from one FPGA to another. The input router receives the plurality of data values and creates a plurality of data streams. The median module receives at least one data stream, increments a plurality of counters corresponding to a single data value within the range of data values, and determines the median by accumulating the contents of each counter. The output transfer module transfers the median to an external destination along with performance statistics of the determination of the median.

Abstract: A method for using a system to compute a solution to a partial differential equation (PDE) broadly comprises the steps of determining the true accuracy required (TAR) to solve the PDE, determining an architecture according to the TAR that performs a plurality of calculations to solve the PDE, determining a time allowed (TA) and a time required (TR) based on the architecture to solve the PDE, rejecting the PDE if the TR is less than or equal to the TA, configuring a plurality of programmable devices with the architecture, initiating the calculations, and ceasing the calculations when an accuracy criteria is met or when the TA expires. The system broadly comprises a plurality of programmable devices, a plurality of storage elements, a device bus, a plurality of printed circuit (PC) boards, and a board to board bus.

Abstract: A computing architecture comprises a plurality of processing elements to perform data processing calculations, a plurality of memory elements to store the data processing results, and a reconfigurable interconnect network to couple the processing elements to the memory elements. The reconfigurable interconnect network includes a switching element, a control element, a plurality of processor interface units, a plurality of memory interface units, and a plurality of application control units. In various embodiments, the processing elements and the interconnect network may be implemented in a field-programmable gate array.

Abstract: An environmentally sealed electronic device with an internal activation circuit that does not require a constant interrogation signal to maintain power to its internal circuitry. The electronic device includes sensor circuitry for gathering or sensing data; an internal battery for powering the sensor circuitry; and an internal activation circuit for activating the sensor circuitry. The sensor circuitry may include a temperature sensor, a location sensor, a signal sensor, a sound detector, a motion sensor, or any other device that senses or gathers data. The battery may be any type of energy storage device such as a lithium or alkaline battery. The activation circuit includes a receiver for receiving a radio frequency signal from an external source and a switch for connecting the battery to the sensor circuitry in response to the receiver. The switch is operable to maintain connection of the battery to the sensor circuitry after the radio frequency signal ceases.

Abstract: A mobile communication device includes a processor; a data acquisition device for acquiring data and providing it to the processor; a transceiver for transmitting at least some of the acquired data to an external device; and a low-power clock. The low-power clock counts down a random delay time period and temporarily shifts the processor and the transceiver from low-power sleep modes to active wake modes so that the processor and transceiver can transmit at least some of the acquired data to the external device while in their active wake modes.

Abstract: A system and method for estimating a geolocation of a non-cooperative target using any reasonable target location estimate. Collectors may acquire actual signal measurements including a direction of arrival (DOA), a target range, a time difference of arrival (TDOA), a range rate, a range sum, and/or a frequency difference of arrival (FDOA). A processing device may receive the actual signal measurements and navigational data regarding the collectors. Then, the processing device may calculate an estimated target location as a solution to a nonlinear optimization problem where an objective function to be minimized is a weighted sum-of-squares of differences between the actual signal measurements and calculated values corresponding to signal measurements that theoretically should be produced for a particular target location. The algorithm used to solve this problem may be a globally convergent algorithm, such as a Levenberg-Marquardt algorithm.

Abstract: Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Dynamically-sized data packets, sized in accordance with the amount of data ready to be sent, are transferred between the devices and/or interfaces on the card.

Abstract: A system for solving linear equations comprises a first circuit including a first multiplication module for multiplying a first row of a matrix by a first instance of a vector variable to generate a first product, and a first linear solver module for calculating an updated first element of the vector variable using the first product. A second circuit includes a second multiplication module for multiplying a second row of the matrix by a second instance of the vector variable to generate a second product, and a second linear solver module for calculating an updated second element of the vector variable using the second product. An interface module updates the second instance of the vector variable with the first updated element, and updates the first instance of the vector variable with the second updated element.

Abstract: A system for identifying at least one phase transition in a phase-shift keying signal comprising a plurality of data samples corresponding to phase values. The system comprises a memory operable to store computing device executable instructions; and a computing device. The computing device is operable to generate a first falling edge region function for each data sample; generate a first rising edge function for each data sample; generate a first level function for each data sample; and generate a second falling edge function for each data sample. The second falling edge function equals the first falling edge function if the first falling edge function is greater than the first rising edge function and the first level function, and the second falling edge function equals zero.

Abstract: A system for correcting image characteristic data from a plurality of pixels comprises at least one field programmable gate array (FPGA), a lookup table, and a correction module. The FPGA may include a plurality of configurable logic elements and a plurality of configurable storage elements. The lookup table may be accessible by the FPGA and may store a plurality of correction components associated with each pixel, including a gain value, an offset value, and a bad pixel value. The correction module may be formed from the configurable logic elements and configurable storage elements and may receive the characteristic data and the correction components. The correction module may generate corrected data for each characteristic data by utilizing the gain value, the offset value, and the bad pixel value.

Abstract: A programmable element for data processing comprises a crosspoint switch (318), a mathematical operation module (320), and a plurality of data hold modules (604,606). Each of the data hold modules (604,606) receives data from the crosspoint switch (318) and communicates the data to an input of the mathematical operation module (320) such that data arrives at the inputs of the mathematical operation module (320) substantially simultaneously. A first data hold module (604) communicates a first data valid signal to a second data hold module (606) upon receipt of first valid data, and the second data hold module communicates a second data valid signal to the first data hold module upon receipt of second valid data.

Abstract: An automatic background noise estimator (BNE) seed calculator for determining a starting point for a BNE circuit which tracks the noise floor received by a receiver. The BNE seed calculator may sample a plurality of data points from the receiver and calculate the magnitude of each point. The seed calculator may then determine the peak magnitude value, a plurality of mean values, and the variance of the sampled points. A plurality of lookup tables are used to compare the peak, mean, and variance values with simulated peak, mean, and variance values to estimate the noise floor level of the actual signal and use that to determine the optimum BNE seed value. Simulation software such as MATLAB is used to develop the lookup tables by simulating peak, mean, and variance values based on a plurality of signal-to-noise ratios (SNR).

Abstract: A method for using a system to compute a solution to a partial differential equation (PDE) broadly comprises the steps of determining the true accuracy required (TAR) to solve the PDE, determining an architecture according to the TAR that performs a plurality of calculations to solve the PDE, determining a time allowed (TA) and a time required (TR) based on the architecture to solve the PDE, rejecting the PDE if the TR is less than or equal to the TA, configuring a plurality of programmable devices with the architecture, initiating the calculations, and ceasing the calculations when an accuracy criteria is met or when the TA expires. The system broadly comprises a plurality of programmable devices, a plurality of storage elements, a device bus, a plurality of printed circuit (PC) boards, and a board to board bus.

Abstract: A fast Fourier transform (FFT) architecture operable to transform data of variable point size includes a plurality of input ports, a plurality of memory elements, a crosspoint switch, a plurality of processing elements, and a plurality of output ports. The inputs ports read time-domain data from an external source. The memory elements store input data, intermediate calculation results, and output data. The crosspoint switch allows data to flow from any one architecture component to any other architecture component. The processing elements perform the FFT calculation. The output ports write frequency-domain data to an external source.

Abstract: A finite impulse response filter comprises an input formatter, a plurality of sample registers, a plurality of coefficient registers, an arithmetic unit, a multiply accumulate unit, a crosspoint switch, an interpolator, a control unit, and an output formatter. The input formatter separates the in-phase portion of a complex-number discrete-time sample from the quadrature portion. The sample registers store a plurality of discrete-time samples. The coefficient registers store a plurality of coefficients. The arithmetic unit adds two of the discrete-time samples to create a sum. The multiply accumulate unit includes a multiplier that multiplies the sum by a coefficient to create a product, an adder that adds the product to a sum of products, and a register that stores the sum of products. The crosspoint switch allows communication between the first and second plurality of registers and the arithmetic unit and the multiply accumulate unit.

Abstract: An apparatus for covertly marking a target includes a housing sized and configured to simulate a portable electronic device; a reservoir positioned in the housing for holding a quantity of miniature markers; and a dispersing mechanism positioned in or on the housing for dispersing the markers onto the target.

Abstract: A system for characterizing a compressed sensing apparatus is described which broadly includes a random vector generator for generating an input vector, a waveform generator in communication with the random vector generator for converting the input vector into an analog signal, a compressed sensing apparatus in communication with the digital-to-analog converter for determining a digital bit stream from the analog signal, a serial-to-parallel converter for converting the digital bit stream into an input vector; and an electronic processor in communication with the random number generator and the serial-to-parallel converter configured for determining a compressed sensing matrix.

Abstract: A system for sorting data and calculating statistics on large data sets with a known value range includes a memory element and a processing element configured to execute steps of the methods. Methods for sorting data include establishing an array of counters such that each counter corresponds to a value in the data set, reading the numbers and incrementing the counter corresponding to the value of each number, and listing the values in sequential order wherein each value occurs in the list according to the count of the corresponding counter. Methods for calculating statistics utilize the count stored in each counter from the sorted data and the value that corresponds thereto.

Abstract: A system for a conjugate gradient iterative linear solver that calculates the solution to a matrix equation comprises a plurality of gamma processing elements, a plurality of direction vector processing elements, a plurality of x-vector processing elements, an alpha processing element, and a beta processing element. The gamma processing elements may receive an A-matrix and a direction vector, and may calculate a q-vector and a gamma scalar. The direction vector processing elements may receive a beta scalar and a residual vector, and may calculate the direction vector. The x-vector processing elements may receive an alpha scalar, the direction vector, and the q-vector, and may calculate an x-vector and the residual vector. The alpha processing element may receive the gamma scalar and a delta scalar, and may calculate the alpha scalar. The beta processing element may receive the residual vector, and may calculate the delta scalar and the beta scalar.

Abstract: A system for evaluating the convergence to a solution for a matrix equation comprises at least one reconfigurable computing device such as a field programmable gate array (FPGA), an update storage element, a conversion element, a summation unit, and a comparator. The FPGA includes a plurality of configurable logic elements and a plurality of configurable storage elements, which are utilized to form the update storage element, the conversion element, the summation unit, and the comparator. The update storage element is configured to store a plurality of updates. The conversion element determines the absolute value of the updates. The summation unit accumulates the absolute values of the updates to produce a total sum, which is compared to a convergence factor by the comparator. Convergence is signaled when the total sum is less than the convergence factor.