Abstract: A method and information storage media having instructions stored thereon for supervised Deep Learning (DL) systems to learn directly from unlabeled data without any user annotation. The annotation-free solutions incorporate a new learning module, the Localization, Synthesis and Teacher/Annotation Network (LSTN) module, which features a data synthesis and generation engine as well as a Teacher network for object detection and segmentation that feeds the processing loop with new annotated objects detected from images captured at the field. The first step in the LSTN module learns how to localize and segment the objects within a given image/scene following an unsupervised approach as no annotations about the objects' segmentation mask or bounding box are provided.

Abstract: Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.

Abstract: Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

Abstract: Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.

Abstract: An automated object data dispensing insertion system including an electronic/mechanical object/data dispensing/insertion device configured to operate by manual contact of a user with the system and is mounted on a support structure. The system further includes at least one sanitizing electromagnetic radiation source mounted on the support structure that is arranged to invest at least part of the electronic/mechanical device and the support structure. The system any include a movable screen associated with the support structure and configured to selectively assume an access position and a protection position in which, respectively, it enables and disables user access to the electronic/mechanical device and at least a portion of the support structure.

Abstract: Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

Abstract: Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.

Abstract: Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.

Abstract: Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.

Abstract: A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

Abstract: Methods of processing images, such as ultrasound images, to determine integrity of an implant are described. The method may include receiving an ultrasound image of an implant in a body of a subject; determining one or more characteristics of a surface of the implant based on an intensity of pixels of the ultrasound image; generating a predicted status of the implant based on the one or more characteristics by comparison of the one or more characteristics with a database of image data; and displaying the predicted status of the implant. The implant may be a breast implant, for example, wherein the method is useful for analyzing the presence or probability of extracapsular ruptures, contractures, and combinations thereof.

Abstract: An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.

Abstract: Methods and systems are described for receiving an input data voltage signal at a first data decision circuit of set of pipelined data decision circuits, receiving an aggregate decision feedback equalization (DFE) correction current signal from a first analog current summation bus, the aggregate DFE correction current signal comprising a plurality of DFE tap-weighted currents from respective other data decision circuits of the set of pipelined data decision circuits, determining a data output decision value based on the received input data voltage signal and the received aggregate DFE correction current signal, and generating at least one outbound DFE tap-weighted current on at least one other analog current summation bus connected to at least one other data decision circuit of the set of pipelined data decision circuits.

Abstract: Aspects of the present disclosure are directed to a medical implant introducer (100) and methods of its use. The introducer (100) may include a handle (120), an implant-holding cavity disposed distally from the handle (120), a fluid supply conduit (122) fluidly coupled to an interior portion of the implant-holding cavity, and a distal nozzle (110) having a proximal portion, a distal portion, a middle portion in between the proximal portion and the distal portion, the middle portion having a tapered profile such that the proximal portion is larger than the distal portion, and a distal opening (112), wherein an implant in the implant-holding cavity may be expelled from the introducer (100) through the distal opening (112).

Abstract: Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

Abstract: Implants having symmetry are described. The implant may comprise a biocompatible material and have at least two planes of symmetry, including symmetry about an equator of the implant. The implant may be a body contouring implant, wherein a posterior side of the implant is symmetric about the equator to an anterior side of the implant.

Abstract: A computer-implemented method for secure identification of a device being associated at a specific location, thus allowing a user to activate a procedure connected to the specific location where the device is placed, said device being disconnected from internet, comprising the following steps: an enrollment process performed through an application miming on a mobile device, said enrollment process associating the device hardware parameters to the specific location and recording and storing these data on a back-end application miming on a central system; a generation process performed on the device, said generation process generating and displaying on the device a graphical code OTP based with limited lifetime; a validation process of the graphical code OTP based; if the received graphical code OTB based is validated, the user is allowed to activate, through his mobile device, the procedure connected to the specific location.

Abstract: Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.

Abstract: A LIDAR system which reduces or suppress the frequency shift induced by the movement of objects in a scene relative to the LIDAR, and which comprises a light source, an input aperture (101), a splitter (2) configured to split a reflected light into a reference channel (4) and a first imaging channel (3), a first imaging optical IQ receiver (5) configured to obtain a first interference signal, a reference optical IQ receiver (6) configured to obtain a reference interference signal, an imaging oscillator (111), configured to be temporarily coherent with the reflected light, at least a mixer (12), connected to the first imaging optical IQ (5) and to the reference optical IQ (6) and configured to obtain a first intermodulation product with a higher frequency and an intermodulation product of interest with its Doppler Shift scaled.

Abstract: Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.