Patents Assigned to Laboratoire Matériaux et Microélectronique de Provence
  • Patent number: 6829170
    Abstract: A memory cell in an EEPROM includes a floating gate transistor that includes a first conducting terminal and a control gate. A method of controlling the memory cell includes setting a state of the memory cell by simultaneously applying voltage pulses of opposite polarities respectively to the first conducting terminal and to the control gate. The voltage pulses including a first portion having a first slope and a second portion having a second slope, wherein the second slope is based upon the polarities of the voltage pulses. The method allows the amplitude of the voltage pulses to be reduced.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: December 7, 2004
    Assignees: STMicroelectronics SA, Laboratoire Matériaux et Microélectronique de Provence
    Inventors: Jean-Michel Mirabel, Rachid Bouchakour, Pierre Canet, Romain Laffont, Juliano Razafindramora
  • Publication number: 20040057265
    Abstract: A memory cell in an EEPROM includes a floating gate transistor that includes a first conducting terminal and a control gate. A method of controlling the memory cell includes setting a state of the memory cell by simultaneously applying voltage pulses of opposite polarities respectively to the first conducting terminal and to the control gate. The voltage pulses including a first portion having a first slope and a second portion having a second slope, wherein the second slope is based upon the polarities of the voltage pulses. The method allows the amplitude of the voltage pulses to be reduced.
    Type: Application
    Filed: July 9, 2003
    Publication date: March 25, 2004
    Applicants: STMicroelectronics SA, Laboratoire Materiaux et Microelectronique de Provence (L2MP)
    Inventors: Jean-Michel Mirabel, Rachid Bouchakour, Pierre Canet, Romain Laffont, Juliano Razafindramora