Abstract: In a method for determining an endpoint in a chemical mechanical planarization (CMP) operation, the concentration of an oxidizing agent in the slurry byproduct generated during the CMP operation is monitored. The endpoint of the CMP operation is determined based on the concentration of the oxidizing agent in the slurry byproduct. The concentration of the oxidizing agent in the slurry byproduct may be monitored by diverting the slurry byproduct from a surface of a polishing pad, and measuring an optical property of the slurry byproduct diverted from the surface of the polishing pad. A CMP system configured to implement the method for determining an endpoint also is described.

Abstract: An apparatus for reducing non-uniform stretch of a belt used in the CMP system is disclosed. The belt that may be used with the apparatus extends between a first roller and a second roller to define a belt loop with an inner surface and an outer surface to be used for CMP. The apparatus includes a compensating roller that has a first end and a second end where the first end and second end extends a width of the belt. The first end and the second end have a first diameter. The center of the roller has a second diameter that is less than the first diameter. The compensating roller has a symmetrically tapered shape that extends between each of the first end and second end to the center. The compensating roller is positioned inside of the belt loop, and is applied to the inner surface of the belt loop to reduce non-uniform stretch of the belt.

Abstract: Apparatus controls the temperature of a wafer for chemical mechanical polishing operations. A wafer carrier wafer mounting surface positions a wafer adjacent to a thermal energy transfer unit for transferring energy relative to the wafer. A thermal energy detector oriented adjacent to the wafer mounting surface detects the temperature of the wafer. A controller is responsive to the detector for controlling the supply of thermal energy relative to the thermal energy transfer unit. Embodiments include defining separate areas of the wafer, providing separate sections of the thermal energy transfer unit for each separate area, and separately detecting the temperature of each separate area to separately control the supply of thermal energy relative to the thermal energy transfer unit associated with the separate area.

Abstract: A semiconductor manufacturing process wherein high aspect ratio deep openings are plasma etched in a dielectric layer using an etchant gas which includes a fluorocarbon, a sulfur-containing gas, an oxygen-containing gas and an optional carrier gas. The etchant gas can include CxFyHz such as C4F8, SO2, O2 and Ar. The combination of the sulfur-containing gas and the oxygen-containing gas provides profile control of the deep openings.

Abstract: A polishing head assembly for use in a chemical mechanical planarization apparatus is provided. The polishing head assembly includes a carrier head shaped substantially like a disk having a circumference, a top surface, a bottom surface, and an outer wall, the outer wall having a groove therein, the groove extending into the carrier head from the bottom surface of the carrier head, and the groove running the entire circumference of the carrier head; and a retainer ring having an interior wall and an exterior wall, the interior wall of the retainer ring being in contact with the outer wall of the carrier head, the interior wall having a slot therein, the slot defining a lower portion of the interior wall as a flexible leg, the flexible leg having a receiving end that is adapted to secure an object having a surface to be polished, the slot having a first terminal end adjacent to the groove in the carrier head and a second terminal end, opposite the first terminal end, in the body of the retainer ring.

Abstract: An invention is provided for detecting an endpoint during a chemical mechanical polishing (CMP) process. A reflected spectrum data sample is received that comprises a plurality of values corresponding to a plurality of spectrums of light reflected from an illuminated portion of a surface of a wafer. The reflected spectrum data sample is decomposed into noise sub-space values and signal sub-space values, and the noise sub-space values are truncated. In addition, outside spectrum data is extrapolated using a linear combination of the values of the reflected spectrum data sample. In this manner, an endpoint can be determined based on optical interference occurring in the reflected spectrum data.

Abstract: An apparatus for chemically mechanically planarizing a semiconductor wafer is disclosed having a continuous polishing strip with first side having a fixed abrasive surface and a second side opposite the first side. In one embodiment, a first drive roller holds a first end of the polishing strip, a second drive roller holds a second end of the polishing strip, and a pair of support rollers contacts the second side of the polishing strip on either end of a polishing strip support. A drive motor is operably connected to the first and second drive rollers for moving the polishing strip in a linear, bi-directional manner.

Abstract: A grid protects a manometer diaphragm from plasma. A plasma chamber is used to generate a plasma. A manometer is used to measure the pressure in the plasma chamber. A grounded electrically conductive grid is used to screen out ions in the plasma before they reach a diaphragm in the manometer. The grid may be formed in a centering ring. A pipe may be used to connect the manometer to the plasma chamber. The centering ring may be placed in the joint in the pipe, with the centering ring and grid being grounded to the pipe.

Abstract: The present invention includes a system and method for confining plasma within a plasma processing chamber. The plasma processing apparatus comprises a first electrode, a power generator, a second electrode, at least one confinement ring, and a ground extension surrounding the first electrode. The first electrode is configured to receive a workpiece and has an associated first electrode area. The power generator is operatively coupled to the first electrode, and the power generator is configured to generate RF power that is communicated to the first electrode. The second electrode is disposed at a distance from the first electrode. The second electrode is configured to provide a complete electrical circuit for RF power communicated from the first electrode. Additionally, the second electrode has a second electrode area that is greater than the first electrode area. At least one confinement ring is configured to assist confine the plasma.

Abstract: An antenna arrangement for generating an electric field inside a process chamber through a window. Generally, the antenna arrangement comprises an outer loop, comprising a first outer loop turn disposed around an antenna axis, an inner loop, comprising a first inner loop turn disposed around the antenna axis, wherein the inner loop is closer to the antenna axis than the outer loop is to the antenna axis in each azimuthal direction, and a radial connector radially electrically connecting the outer loop to the inner loop, wherein the radial connector is placed a large distance from the window.

Abstract: CMP methods reduce a cause of differences between an edge profile of a chemical mechanical polished edge of a wafer and a center profile of a chemical mechanical polished central portion of the wafer within the edge. The wafer is mounted on a carrier surface of a wafer carrier so that a wafer axis of rotation is gimballed for universal movement relative to a spindle axis of rotation of a wafer spindle. An operation using a retainer ring limits wafer movement on the carrier surface perpendicular to the wafer axis. Another operation limits a direction of permitted movement between the wafer carrier and the retainer ring to only movement parallel to the wafer axis, so that a wafer plane and a retainer ing may be co-planar.

Abstract: A vacuum plasma processor includes an electrode array with plural mutually-insulated electrodes forming a bottom or top electrode of the plasma processor. When the electrode array is part of the bottom electrode, the electrodes of the array are parts of a thermoelectric, Peltier effect arrangement responsive to localized temperature sensors and are parts of an electrostatic chuck. The thermoelectric arrangement controls localized temperature of workpieces and the chucking voltages indicate workpiece position relative to a workpiece holder including the electrodes. The electrodes of the arrays are coupled to circuitry for determining and/or controlling at least one localized plasma electric parameter at different locations of a workpiece and/or the plasma. The circuitry simultaneously supplies RF power having differing frequencies and/or power levels to different electrodes of the arrays and includes separate matching networks connected to the different electrodes of the array.

Abstract: Apparatus and methods control the temperature of a wafer for chemical mechanical polishing operations. A wafer carrier has a wafer mounting surface for positioning the wafer adjacent to a thermal energy transfer unit for transferring energy relative to the wafer. A thermal energy detector is oriented adjacent to the wafer mounting surface for detecting the temperature of the wafer. A controller is responsive to the detector for controlling the supply of thermal energy relative to the thermal energy transfer unit. Embodiments include defining separate areas of the wafer, providing separate sections of the thermal energy transfer unit for each separate area, and separately detecting the temperature of each separate area to separately control the supply of thermal energy relative to the thermal energy transfer unit associated with the separate area.

Abstract: A method for fabricating a pad, a belt, or other polishing surface for use in chemical mechanical planarization (CMP) system is provided. The method includes providing a supporting mesh, a first polymeric material over the supporting mesh and a second material such that the mesh is encased between the first polymeric material and the second material. The first polymeric material, the supporting mesh, and the second material are then bonded together.

Abstract: A method for cleaning top and bottom surfaces of a semiconductor substrate is provided. The method includes scrubbing top and bottom surfaces of the semiconductor wafer with top and bottom brushes, respectively. Top and bottom brushes are saturated and supplied with a scrubbing fluid. The top and bottom brushes are squeezed so as to press out excess scrubbing fluid by continuing to apply top and bottom brushes against top and bottom surfaces of the semiconductor substrate, respectively, but without supplying the scrubbing fluid. Top and bottom brushes are respectively moved away from the top and bottom surfaces of the semiconductor substrate. The top brush is rotated so as to prevent dripping onto the top surface of the semiconductor substrate. Top and bottom surfaces of the semiconductor substrate are rinsed using a rinse fluid while continuing to rotate the top brush that was squeezed to press out the excess scrubbing fluid.

Abstract: A method and system for processing a wafer is disclosed. The method includes receiving a wafer having a process side and a backside. The method further includes removing un-wanted particles from the backside of the wafer to prevent gaps from forming between the backside of the wafer and a chucking surface. The method also includes performing a specific processing task on the process side of the wafer after cleaning the backside of the wafer.

Abstract: An apparatus enabling preparation and use of a fixed abrasive polishing member is described. The apparatus includes a patterned three-dimensional substrate, an abrasive coating a surface of the patterned substrate and a vacuum deposition chamber in which the abrasive is applied to the surface of the substrate. In addition, rather than a fixed abrasive, non-abrasive material may be applied to the surface of the patterned substrate, in which case, a conventional slurry may be used in planarization of an applied semiconductor wafer.

Abstract: An adjustable RF coupling ring is capable of reducing a vertical gap between a substrate and a hot edge ring in a vacuum processing chamber. The reduction of the gap reduces polymer deposits on the substrate and electrostatic chuck and improves wafer processing.

Abstract: An apparatus and method for etching a feature in a wafer with improved depth control and reproducibility is described. The feature is etched at a first etching rate and then at a second etching rate, which is slower than the first etching rate. An optical end point device is used to determine the etching depth and etching is stopped so that the feature has the desired depth. Two different etching rates provides high throughput with good depth control and reproducibility. The apparatus includes an etching tool in which a chuck holds the wafer to be etched. An optical end point device is positioned to measure the feature etch depth. An electronic controller communicates with the optical end point device and the etching tool to control the tool to reduce the etch rate part way through etching the feature and to stop the etching tool, so that that the feature is etched to the desired depth.

Abstract: MOS transistor formed on a semiconductor substrate of a first conductivity type and method of fabrication are provided. The device includes (a) an interfacial layer formed on the substrate; (b) a high dielectric constant layer covering the interfacial layer that comprises a material that is selected from the group consisting of Ta2O5, Ta2(O1−xNx)5 wherein x ranges from greater than 0 to 0.6, a solid solution of (Ta2O5)r—(TiO2)1−r wherein r ranges from about 0.9 to 1, a solid solution (Ta2O5)s—(Al2O3)1−s wherein s ranges from 0.9 to 1, a solid solution of (Ta2O5)t—(ZrO2)1−t wherein t ranges from about 0.9 to 1, a solid solution of (Ta2O5)u—(HfO2)1−u wherein u ranges from about 0.9 to 1, and mixtures thereof wherein the interfacial layer separates the high dielectric constant layer from the substrate; (b) a gate electrode having a width of less than 0.