Abstract: An apparatus for cleaning a semiconductor substrate is provided. In embodiment of the present invention, a megasonic cleaner capable of providing localized heating is provided. The megasonic cleaner includes a transducer and a resonator. The resonator is configured to propagate energy from the transducer. The resonator has a first and a second end, the first end is operatively coupled to the transducer and the second end is configured to provide localized heating while propagating the energy from the transducer. A system for cleaning a semiconductor substrate through megasonic cleaning and a method for cleaning a semiconductor substrate is also provided.

Abstract: A processing belt for use in chemical mechanical planarization (CMP), and methods for making the same, are provided. Embodiments of the processing belt include a polymeric material reinforced with a woven fabric or synthetic material encased between the polymeric material and an additional polymeric material layer to define the processing belt. The processing belt is fabricated so that the woven fabric forms a continuous loop and is positioned against a surface of the polymeric material. The additional polymeric material layer is applied over the woven fabric, permeating the woven fabric to bond to the polymeric material forming an integral structure of woven fabric reinforced polymeric material.

Abstract: A plasma cleaning method for removing deposits in a CVD chamber. The method includes introducing a cleaning gas comprising a fluorine-based gas into the chamber. A plasma is formed by exposing the cleaning gas to an inductive field generated by resonating a radio frequency current in a RF antenna coil. A plasma cleaning step is performed by contacting interior surfaces of the chamber with the plasma for a time sufficient to remove the deposits on the interior surfaces. An advantage of the plasma cleaning method is that it allows for in-situ cleaning of the chamber at high rates, thereby effectively reducing equipment downtime. The method has particular applicability in the cleaning of a PECVD process chamber.

Abstract: A method and apparatus for conditioning a polishing pad is described. The method includes applying a stream of pressurized liquid to the polishing pad, and removing a significant amount of slurry and liquid from the polishing pad using a vacuum. The apparatus includes a liquid distribution unit forming at least one opening upon which liquid is forced through at high pressure, the opening directed at the polishing pad, and a liquid recovery unit positioned downstream from the liquid distribution unit and in communication with the polishing pad, the liquid recovery unit connected with a vacuum for removing liquid and slurry from the polishing pad.

Abstract: A cascaded disk scrubbing system and method are provided. The cascaded disk scrubbing system includes an array of rows of brush pairs. Each row includes a plurality of counter-rotating brush pairs that are arranged horizontally and longitudinally, and configured to receive and process a disk in a vertical orientation through disk preparation zones defined by each pair of brushes. Below and between the pairs of brushes is a track that is configured to apply a rotation to the disk and to transition the disk in a vertical orientation through the brush pairs. Nozzles dispense fluids on and over the brush pairs, and the brush pairs are configured such that fluids are dispensed through the brush pairs. Nozzles dispense a curtain of fluid between each disk preparation zone, and the cascaded disk scrubbing system is configured to progress from dirtiest to cleanest as the disk transitions through each disk preparation zone.

Abstract: Dynamic alignment of a wafer with a blade that carries the wafer involves determination of an approximate value of wafer offset with respect to a desired location of the wafer in a module. This determination is made using an optimization program. The wafer is picked up from a first location using an end effector that transfers the picked up wafer from the first location past sensors to produce sensor data. For an unknown wafer offset, the picked up wafer is misaligned with respect to a desired position of the picked up wafer on the end effector. When the desired position does not correspond to original target coordinates to which the end effector normally moves, the original target coordinates are modified to compensate for the approximate value of the offset and the picked up wafer is placed at the modified target coordinates to compensate for the unknown offset and the misalignment.

Abstract: A drip manifold having drip nozzles configured to form controlled droplets is provided for use in wafer cleaning systems. The drip manifold includes a plurality of drip nozzles that are secured to the drip manifold. Each of the plurality of drip nozzles has a passage defined between a first end and a second end. A sapphire orifice is defined within the passage and is located at the first end of the drip nozzle. The sapphire orifice is angled to produce a fluid stream that is reflected within the passage and toward the second end to form one or more uniform drops over a brush.

Abstract: A method for using a monitor substrate to determine effectiveness of a cleaning operation is provided. The method includes selecting a substrate from a lot of substrates and inspecting a surface of the substrate to determine a roughness profile of the substrate. The monitor substrate is then processed through a cleaning operation, and the monitor substrate is patterned with die regions throughout. Each of the die regions has a plurality of areas defining distinct roughness simulations. The method the proceeds to inspecting the monitor substrate at one die region and at one of the plurality of areas in the one die region that most closely resembles the roughness profile of the substrate. The inspecting of the monitor substrate is configured to yield data regarding cleaning performance of the cleaning operation.

Abstract: A chamber for transitioning a semiconductor substrate between modules operating at different pressures is provided. The chamber includes a base defining an outlet. The outlet permits removal of an atmosphere within the chamber to create a vacuum. A substrate support for supporting a semiconductor substrate within the chamber is included. A chamber top having an inlet is included. The inlet is configured to allow for the introduction of a gas into the chamber to displace moisture in a region defined above the substrate support. Sidewalls extending from the base to the chamber top are included. The sidewalls include access ports for entry and exit of a semiconductor substrate from the chamber. A method for conditioning an environment above a region of a semiconductor substrate within a pressure varying interface is also provided.

Abstract: A processing belt for use in chemical mechanical planarization (CMP), and methods for making the same, is provided. Embodiments of the processing belt include a mesh belt, and a polymeric material encasing the mesh belt to define the processing belt. The processing belt is fabricated so that the mesh belt forms a continuous loop within the polymeric material, and the mesh belt is constructed as a grid of intersecting members. The intersecting members are joined at fixed joints to form a rigid support structure for the processing belt.

Abstract: A method for optimizing the planarizing length of a polishing pad is disclosed that includes forming a substantially constant network of islands and trenches into a first side of a polishing pad. The trenches are formed to a pre-determined distance apart. The polishing pad is fit to a chemical-mechanical polishing system. A surface layer of a semiconductor wafer is planarized with the first side of the polishing pad. Upon completion of the polishing process, the planarized wafer surface layer is observed. If the wafer surface layer is planarized to an amount outside of a set target polishing range, the distance between the trenches on the first side of the polishing pad is uniformly decreased. The above steps are repeated until the wafer surface layer is planarized to an amount within the set target polishing range.

Abstract: An apparatus and method for in-situ monitoring of thickness during chemical-mechanical polishing (CMP) of a substrate using a polishing tool and a film thickness monitor. The tool has an opening placed in it. The opening contains a monitoring window secured in it to create a monitoring channel. A film thickness monitor (comprising an ellipsometer, a beam profile reflectometer, or a stress pulse analyzer) views the substrate through the monitoring channel to provide an indication of the thickness of a film carried by the substrate. This information can be used to determine the end point of the CMP process, determine removal rate at any given circumference of a substrate, determine average removal rate across a substrate surface, determine removal rate variation across a substrate surface, and optimize removal rate and uniformity.

Abstract: In a linear chemical mechanical planarization (CMP) system, a surface of each roller of a pair of rollers is disclosed which includes a first set of grooves covering a first portion of the surface of the roller where the first set of grooves has a first pitch that angles outwardly toward a first outer edge of the roller. The surface also includes a second set of grooves covering a second portion of the surface of the roller where the second set of grooves has a second pitch that angles outwardly toward a second outer edge of the roller with the second pitch angling away from the first pitch. The surface further includes a first set of lateral channels arranged along the first portion, and a second set of lateral channels arranged along the second portion. The first set of lateral channels crosses the first set of grooves, and the second set of lateral channels crosses the second set of grooves.

Abstract: A central controller for use in a semiconductor manufacturing equipment integrates a plurality of controllers with an open architecture allowing real-time communication between the various control loops. The central controller includes at least one central processing unit (CPU) executing high level input output (i/o) and control algorithms and at least one integrated i/o controller providing integrated interface to sensors and control hardware. The integrated i/o controller performs basic i/o and low level control functions and communicates with the CPU through a bus to perform or enable controls of various subsystems of the semiconductor manufacturing equipment.

Abstract: A corrosion resistant component of semiconductor processing equipment such as a plasma chamber comprises zirconia toughened ceramic material as an outermost surface of the component. The component can be made entirely of the ceramic material or the ceramic material can be provided as a coating on a substrate such as aluminum or aluminum alloy, stainless steel, or refractory metal. The zirconia toughened ceramic can be tetragonal zirconia polycrystalline (TZP) material, partially-stabilized zirconia (PSZ), or a zirconia dispersion toughened ceramic (ZTC) such as zirconia-toughened alumina (tetragonal zirconia particles dispersed in Al2O3). In the case of a ceramic zirconia toughened coating, one or more intermediate layers may be provided between the component and the ceramic coating. To promote adhesion of the ceramic coating, the component surface or the intermediate layer surface may be subjected to a surface roughening treatment prior to depositing the ceramic coating.

Abstract: A method for etching features in an integrated circuit wafer, the wafer incorporating at least one dielectric layer is provided. Generally, the wafer is disposed within a reaction chamber. An etchant gas comprising a hydrocarbon additive and an active etchant is flowed into the reaction chamber. A plasma is formed from the etchant gas within the reaction chamber. The feature is etched in at least a portion of the dielectric layer.

Abstract: An asymmetric double-sided substrate scrubber is provided. The asymmetric double-sided substrate scrubber includes a first roller and a second roller. The first roller is constructed from a first material having a first density and the second roller is constructed from a second material having a second density. The second density is designed to be greater than the first density. The first roller is designed to be applied onto a first side of a substrate with a first force and the second roller is designed to be applied onto a second side of the substrate with a second force. The second force is configured to be substantially equivalent to the first force.

Abstract: A method scales plasma process settings from a first processing device to a second processing device. The first processing device has a first geometry and a first set of process parameters. The second processing device has a second geometry and a second set of process parameters. A first set of plasma process settings that generates the first set of process parameters of the first processing device having the first geometry is determined. The first set of plasma process settings is reduced to isolate at least one variable on which the first set of plasma process settings depends on for each plasma process setting. A scaling factor is calculated for each plasma process setting from the first set of plasma process settings such that the first set of process parameters substantially equals the second set of process parameters.

Abstract: Liquid is removed from wafers for drying a wafer that has been wet in a liquid bath. The wafer and the bath are separated at a controlled rate as the wafer is positioned in a gas-filled volume. The controlled rate is generally not less than the maximum rate at which a meniscus will form between the liquid bath and the surface of the wafer when the liquid bath and the wafer are separated. The gas-filled volume is defined by a hot chamber that continuously transfers thermal energy to the wafer in the gas-filled volume. Hot gas directed into the volume and across the wafer and out of the volume continuously transfers thermal energy to the wafer.

Abstract: A semiconductor manufacturing process wherein an organic antireflective coating is etched with an O2-free sulfur containing gas which provides selectivity with respect to an underlying layer and/or minimizes the lateral etch rate of an overlying photoresist to maintain critical dimensions defined by the photoresist. The etchant gas can include SO2 and a carrier gas such as Ar or He and optional additions of other gases such as HBr. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.