Abstract: A fiber-optic to twisted pair data translator configured to be disposed within a wall and thus become part of the building, which further includes a central data distribution facility, such as a communication closet and connecting fiber-optic cables to create a totally integrated structured premise wiring which provides the tenant occupant with the advantages of high-bandwidth fiber-optic communication by a simple twister-pair connection. Moreover, the in-wall data translator according to the present invention provides data format converting intelligence at the wall plate and may be internally or externally powered to maximum flexibility in network architecture while minimizing the building installation costs and inventory of data network components.

Abstract: A bi-directional network medium translator and automatic redundant media data path switch connected between two dissimilar network media, e.g. Fiber Optic (FX) and a plurality of Twisted Pair (TX) data paths, comprising a transceiver and a clock recovery element for each medium, a multiplexer which selectively connects one of said redundant data paths according to a detected master data path failure, and a bi-directional scrambler/descrambler which receives, processes and transmits the data while in the serial data format. Thus, the apparatus according to the present invention is operable to the maximum data rates currently used, provides significantly reduced data delay and reduced lost data due to data path failures and lengthy path switchover times, and may be field-modified to a variety of different media.

Abstract: A high speed data network having a novel data translator having an SRAM data buffer in the full to half duplex direction and flow control media access elements, such as for detecting data collision and retransmission of data, for providing transparent high data rate transfer between full and half duplex data media. The main SRAM data buffer provides multiple frame FIFO storage and configured to provide alternating incoming and outgoing data access. The preferred embodiment further includes main SRAM incoming FIFO and outgoing FIFO memories. The outgoing FIFO memory is configured to operate in an alternating in/out memory access (independent of the main SRAM incoming and outgoing data access) providing data byte access after the byte is written from the main SRAM. Furthermore, the outgoing FIFO memory supplies the data to be retransmitted in the event of a data collision, without interrupting the operation(s) of the main SRAM buffer.