Abstract: According to one embodiment, a content addressable memory (CAM) (100) includes a number of sections (106-1 to 106-i) having data value entries that can be compared to comparand values and/or comparand value portions. Each section (106-1 to 106-i) has an independently configurable width.

Abstract: A CAM cell array (100) that can provide a longest prefix matching operation without necessarily requiring data values to be stored in a particular order. A comparand value can be applied to a CAM cell array (100) to generate ternary match indications. The mask/prefix data values of ternary match indications can be combined to generate a longest prefix value. The longest prefix value can be compared with the mask/prefix data values of the ternary match indications to indicate a data value having a longest prefix match with the comparand value.

Abstract: A content addressable memory that may have reduced charge consumption when switching compare lines is disclosed. According to one embodiment, a content addressable memory (CAM) (300) with paired compare lines (CMP and CMP\) can include an equalization circuit (320) between the two compare lines (CMP and CMP\). An equalization circuit (320) can enter a low-impedance mode when an equalization control signal (EQU\) is in one state and enter a high-impedance mode when an equalization control signal (EQU\) is in another state. An equalization control signal (EQU\) may be governed by an output pulse of a transition detector (312).

Abstract: A ternary CAM (100) includes a CAM cell array (102) arranged into groups (108-1 to 108-5) for storing data values having a predetermined prefix length. The groups (108-1 to 108-5) are arranged in an order that allows for longest prefix match searches. A prefix length translator (104) can receive prefix length values and translate them into corresponding CAM cell array addresses (CAM_ADD). Thus, a prefix value and corresponding data value can be applied to the CAM (100) and the data value can be written into the group (108-1 to 108-5) corresponding to its prefix length. In this way, a table update operation can be performed without having to reorder entries in the ternary CAM (100).

Abstract: A combinational encoder (100) according to one embodiment is disclosed. The combinational encoder (100) can be used with an address encoder (300) to provide a compact priority encoder. The combinational encoder (300) receives a number of input signals (MATCH_IN0-MATCH_IN3) and provides a like number of output signals (MATCH_OUT0-MATCH_OUT3). Unlike a conventional priority encoder, which activates a single output signal in response to various input signal combinations, the combinational encoder (100) provides multiple active output signals in response to particular combinations of input signals. When applied to an appropriate address encoder (300), the multiple active output signals generate address values reflecting the desired priority of the input signals.

Abstract: According to one embodiment, a priority encoder (PE)/read-only-memory (ROM) combination circuit (200) includes detect circuits (206-xy) and passgate circuits (208-xy) arranged into rows (202-x) and columns (202-y). Detect circuits (206-xy) of the same column can be activated by a corresponding input signal (M0 to M7). When a detect circuit (206-xy) of a column (202-y) is activated, the passgates (208-xy) of the same column are disabled, preventing any lower priority active input signals (M0 to M7) from propagating further into the circuit.

Abstract: A modified binary content addressable memory (CAM) (700) having a fast variable prefix matching capability is disclosed. The modified CAM (700) includes modified CAM cells (702(0,0) to 702(n,m)), each of which includes a store/compare circuit (704(0,0) to 704(n,m)) for storing a data value and comparing the data value to a comparand value. In addition, each modified CAM cell (702(0,0) to 702(n,m)) further includes a multiplexer (MUX) circuit (706(0,0) to 706(n,m)). Each MUX circuit (706(0,0) to 706(n,m)) receives a non-shifted comparand value from a modified CAM cell of a previous row and same column, and a shifted comparand value from a modified CAM cell of the previous row and an adjacent column. The MUX circuits (706(0,0) to 706(n,m)) enable a comparand value to be shifted as it is applied to consecutive data values.

Abstract: A content addressable memory (CAM) that is capable of providing multiple word matching is disclosed. According to one embodiment, a CAM (200) includes a word array (206) of data word registers (208-0 to 208-ni). Each data word register (208-0 to 208-ni) provides a word match value (MATCH0-MATCHni) that indicates if an applied comparand value is the same as a data word stored within a data word register (208-0 to 208-ni). Word match values (MATCH0-MATCHni) are received by a match detect circuit (202) that provides a number of encoding values (ENC0-ENCni). In a single word match mode, a comparand value is applied and the encoding values (ENC0-ENCni) can represent single word match values. In a multiple word match mode, a sequence of comparand values are applied and the resulting word match values stored. The resulting encoding values (ENC0-ENCni) can represent the logical combination of multiple word match values.

Abstract: According to one embodiment a content addressable memory (CAM) (100) can segment comparand values and data values into portions. Comparand value portions are compared with corresponding data value portions in sequential compare operations. Sequential compare operations can distribute current peaks over two or more compare operations, thereby reducing peak current transients.

Abstract: According to one embodiment, a multiple signal detect circuit (100) can include a detect node (102) and a reference node (104). The potential of the detect node (102) can be discharged (or charged) at a rate that depends upon the number of active input signals (M1 to Mn). The potential of the reference node (104) can be discharged (or charged) at a reference rate. The reference rate can be greater than the rate at which the detect node (102) is discharged (or charged) when one input signal is activated, and less than the rate at which the detect node (102) is discharged (or charged) when two input signals are activated. A differential voltage between the detect node (102) and reference node (104) can be amplified by an amplifier (110).

Abstract: A content addressable memory (CAM) includes a number of novel CAM cells that can be switchable between a binary mode of operation and a ternary mode of operation. According to one embodiment, a novel CAM cell (100) can include a switchable impedance path (104) arranged in series with a compare circuit (110). A switchable impedance path (104) can include a first impedance path (106) arranged in series with a second impedance path (108). The first impedance path (106) can be controlled by a mode value (MODE) and the second impedance path (108) can be controlled by a mask value (/M).

Abstract: A ternary content addressable memory (CAM) (800) having a massive, parallel shift capability is disclosed. The CAM (800) includes an array of CAM cells (802(1,1) to 802(1,4)), each of which includes a data value register (804(1,1) to 804(1,4)) and a mask value register (806(1,1) to 806(1,4)). To enable parallel shifting between a CAM cell in one row with a corresponding CAM cell in a higher row, each data value register (804(1,1) 804(1,4)) and mask value register (806(1,1) to 806(1,4)) includes an upper data input (UD) coupled the output of a CAM cell in the higher row. To enable parallel shifting between a CAM cell in one row with a corresponding CAM cell in a lower row, each data value register (804(1,1) 804(1,4)) and mask value register (806(1,1) to 806(1,4)) includes a lower data input (LD) coupled the output of a CAM cell in the lower row.