Abstract: A signal multiplexer system and a signal latch system for low voltage (Vdd≈1.2 volts) and high speed transitions between states. A dc signal isolation circuit, inserted between a clock signal circuit and a signal input/output circuit, allows use of a two-transistor-layer vertical structure that provides adequate headroom voltage (about 0.3-0.4 volts, or larger) for high speed transistor response.

Abstract: An integrated circuit includes standard cells interspersed with islands of spare gates. The spare gates are arranged in multiple groups of spare gates, with each group of spare gates within a corresponding designated spare gate area of a standard cell portion of the integrated circuit. At least a given one of the groups of spare gates is arranged between first and second rows of the standard cells and includes one or more rows of spare gates, with each row of spare gates including multiple base transistor structures arranged adjacent to one another along longitudinal dimensions of the structures. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool. The spare gates may be implemented using a base transistor structure compatible with the standard cell CAD tool.

Abstract: A method of self-testing the programmable routing network in a field programmable gate array (FPGA) during normal on-line operation includes configuring the FPGA into an initial self-testing area and a working area. The initial self-testing area is preferably configured to include an horizontal self-testing area primarily for testing horizontal wire segments and a vertical self-testing area primarily for testing vertical wire segments. Programmable logic blocks located within the self-testing areas are configured to function as a test pattern generator and an output response analyzer, and a portion of the programmable routing resources within the self-testing areas is configured as groups of wires under test. An exhaustive set of test patterns generated by the test pattern generator is applied to the groups of wires under test which are repeatedly reconfigured in order to completely test the programmable routing resources within the self-testing areas.

Abstract: A method of self-testing the programmable logic blocks of field programmable gate arrays (FPGAs) during normal on-line operation includes configuring the FPGA into an initial self-testing area and a working area. The self-testing area may be further subdivided into self-testing tiles for concurrent testing if desired. The programmable logic blocks located within the self-testing area or self-testing tiles are established to function as a test pattern generator, an output response analyzer, and equivalently configured programmable logic blocks under test for testing. An exhaustive set of test patterns generated by the test pattern generator are applied to the programmable logic blocks under test which are repeatedly reconfigured in order to completely test the programmable logic blocks in all possible modes of operation.

Abstract: For use with a programmable clock manager (PCM), a selection system and method of generating a clock signal. In one embodiment, the selection system includes a phase selector, having multiple taps, configured to generate multiple phase shifted signals from a reference signal corresponding to an input signal with a fixed phase shift therebetween. The phase selector is further configured to select at least two of the phase shifted signals. The selection system further includes a duty cycle synthesis circuit configured to generate a clock signal having a duty cycle as a function of a phase shift between the selected phase shifted signals.

Abstract: A CMOS Schmitt Trigger circuit design provides a relatively high speed device having a tight, substantially monotonic hysteresis characteristic which is substantially independent of fabrication process parameters and can be used with relatively wide power supply designs, including operating a relatively low Vcc. Tight trip point variation is maintained in conjunction with process, voltage, and temperature changes. The circuit is adaptable for forming an integrated circuit buffer element.

Abstract: A sense amplifier is provided that mitigates the effect of threshold voltage mismatch within the sense amplifier. The sense amplifier has an inverter pair coupled to the input terminals, with a resistive element coupled across output terminals of the inverter pair. Inverter gain stages following the inverter pair are coupled to a current limiting circuit to monitor and limit the current flowing through the inverter gain stage immediately following the inverter pair. The current limiting circuit allows the sense amplifier to be biased such that speed is improved while limiting power dissipation to acceptable levels, even under undesirable process, temperature, and power supply variations.

Abstract: A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portions of the programmable logic device.

Abstract: An improved EEPROM cell structure and a method of fabricating the same is provided so as to improve data retention. The EEPROM cell includes a stacked dielectric structure consisting of a thin tunnel oxide layer and a high-k dielectric layer to function as the tunneling dielectric barrier so as to suppress leakage current.

Abstract: An in-system programmable (ISP) system, having a plurality of ISP devices, can be programmed by remote access from a host controller. The remote access can be accomplished over a wired data network, a wireless data network such as an infra-red data network and a radio wave data network, or a hybrid network including both a wired data network portion and a wireless data network portion. An access interface connects the host controller to an ISP programmer over the wired or wireless communication link. The ISP programmer programs the ISP system in accordance with ISP programming conventions. The ISP programmer can be provided by an integrated circuit having a microprocessor core.

Abstract: An active termination resistor is provided within a feedback loop circuit thus advantageously increasing the stability of the feedback loop circuit. In particular, the active termination resistor traces the impedance of the feedback loop such that R(f).congruent.1/GM3(f). The active resistor may also be configured to track the value of the resistor to set the feedback transconductance over process and temperature variations to ensure stability of the feedback loop over these variations.

Abstract: A programmable analog circuit apparatus receives a differential analog input signal and provides a processed differential analog output signal. The programmable analog circuit apparatus includes a first input transconductor, a differential amplifiers, and a feedback transconductor. The first input transconductor has a programmable transconductance and includes an input transconductor positive input terminal and an input transconductor negative input terminal and an input transconductor positive output terminal and an input transconductor negative output terminal. The positive and negative input terminals are coupled to receive the differential analog input signal. The differential amplifier includes first and second amplifier input terminals and first and second amplifier output terminals. The positive and negative input transconductor output terminals are coupled to the first and second differential amplifier input terminals.

Abstract: A programmable logic device is disclosed which is adapted to isolate the Miller capacitances of erased memory cells from the product terms and to limit the cell current drawn through the product term sense amplifiers. The invention substantially reduces the row switching noise coupled onto the product terms, allows high speed sense amplifier operation, and significantly reduces the power dissipated by the device. In accordance with the invention, the electrically erasable sense transistor for each memory cell is disposed between the cell select transistor and the product term sense amplifier, thereby isolating the Miller capacitance associated with the select transistor from the sense amplifier when the cell is in the erased (nonconductive) state. Separate product term ground lines are provided for each product term.