Abstract: A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.
Type:
Application
Filed:
March 18, 2003
Publication date:
September 23, 2004
Applicant:
Lattice Semiconductor Corporation, a Delaware corporation
Inventors:
John A. Schadt, William B. Andrews, Zheng Chen, Anthony K. Myers, David A. Rhein, Warren L. Ziegenfus, Fulong Zhang, Ming Hui Ding, Larry R. Fenstermaker