Abstract: In one embodiment of the invention, a computer-implemented method of configuring a programmable logic device (PLD) includes placing logical functions within logical resources of the PLD to implement a desired netlist; swapping the logical function of at least one logical resource with the logical function of at least one other logical resource within the PLD; and evaluating whether to accept or reject the swap using a simulated annealing process that calculates at least three cost function values based upon routing priority groups, timing priority groups, and a timing critical group.

Abstract: A clock generator has a reset circuit and (at least) two dividers, where each divider divides a reference clock signal by a divisor value to generate an output clock signal. The reset circuit generates reset signals for the dividers, where the reset signals are delayed relative to one another by a selected number of reference clock cycles, such that the dividers generate output clock signals having a desired phase offset between them.