Abstract: A duplexing structure of a switching system processor in which a duplexing channel is formed through a back plane to implement duplexing in an active mode and a standby mode includes first and a second processor boards for which a duplexing channel is formed through a back plane and being dually operated in an active mode and in a standby mode, wherein each processor bus connected to a microprocessor of a processor board at one side, and a duplexing channel connected to a processor board at the other use a different clock so that the two processor boards are independently operated.