Abstract: The method for evaluating the compactness of a layer of railroad ballast near a railroad tie includes at least one step of taking at least two measurements (11,11a,11b) of the penetration resistance (Qd) of the ballast (13) near one and the same railroad tie (10), and a step of calculating the mean value (Qdmean) of these measurements (11,11a,11b) of penetration resistance (Qd). Also provided are a device for implementing such a method and a method for predicting the settlement of the ballast of a railroad track including a step of evaluating the compactness of a ballast near a railroad tie.
Type:
Grant
Filed:
October 28, 2013
Date of Patent:
November 7, 2017
Assignees:
SNCF RESEAU, UNIVERSITE DE MONTPELLIER 2 SCIENCES ET TECHNIQUES, UNIVERSITE BLAISE PASCAL-CLERMONT II, LE CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)
Inventors:
Gilles Saussine, Juan Carlos Quezada, Pierre Breul, Franck Radjai
Abstract: The method for evaluating the compactness of a layer of railroad ballast near a railroad tie includes at least one step of taking at least two measurements (11,11a,11b) of the penetration resistance (Qd) of the ballast (13) near one and the same railroad tie (10), and a step of calculating the mean value (Qdmean) of these measurements (11,11a,11b) of penetration resistance. Also provided are a device for implementing such a method and a method for predicting the settlement of the ballast of a railroad track including a step of evaluating the compactness of a ballast near a railroad tie.
Type:
Application
Filed:
October 28, 2013
Publication date:
October 15, 2015
Applicants:
SOCIETE NATIONALE DES CHEMINS DE FER FRANCAIS SNCF, UNIVERSITE DE MONTPELLIER 2 SCIENCES ET TECHNIQUES, UNIVERSITE BLAISE PASCAL- CLERMONT II, LE CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)
Inventors:
Gilles Saussine, Juan Carlos Quezada, Pierre Breul, Franck Radjai
Abstract: An ESD protection device, which is arranged to be active at a triggering voltage (Vt1) for providing ESD protection, comprises a first region of the first conductivity type formed in a semiconductor layer of the first conductivity type, the first region extending from a surface of the semiconductor layer and being coupled to a first current electrode (C) of the semiconductor device, a well region of a second conductivity type formed in the semiconductor layer extending from the surface of the semiconductor layer, and a second region of the second conductivity type formed in the well region, the second region being coupled to a second current electrode (B). The ESD protection device further comprises a floating region of the second conductivity type formed in the semiconductor layer between the first current electrode (C) and the well region and extending from the surface of the semiconductor layer a predetermined depth.
Type:
Grant
Filed:
May 4, 2007
Date of Patent:
January 6, 2015
Assignees:
Freescale Semiconductor, Inc., Le Centre National de la Recherché Scientifique (CNRS)
Inventors:
Philippe Renaud, Patrice Besse, Amaury Gendron, Nicolas Nolhier
Abstract: A flight control system includes at least one actuator for a mobile flight surface of an aircraft, and a flight control module in communication with the actuator. The module includes a first and a second computer. Each computer calculates a control command established according to at least one predetermined law for control of the flight surface. The first computer, known as validating computer, comprises logic means adapted for comparing its control command with that of the second computer, known as master computer, and for transmitting the result of the comparison to the actuator. The actuator comprises logic means adapted for deciding, on the basis of the result, to execute or not to execute the command of the master computer. An aircraft comprising such a system is also disclosed.
Type:
Grant
Filed:
January 20, 2010
Date of Patent:
August 12, 2014
Assignees:
Airbus Operations S.A.S., Le Centre National de la Recherche Scientifique (CNRS)