Abstract: A method of manufacturing a silicon nitride film that forms a silicon nitride film on a surface of a substrate comprises sequentially repeating first through third steps. The first step includes feeding a first gas containing silicon and nitrogen to the surface of the substrate. The second step includes feeding a second gas containing nitrogen to the surface of the substrate. The third step includes feeding a third gas containing hydrogen to the surface of the substrate.

Abstract: A method of manufacturing a silicon nitride film that forms a silicon nitride film on a surface of a substrate comprises sequentially repeating first through third steps. The first step includes feeding a first gas containing silicon and nitrogen to the surface of the substrate. The second step includes feeding a second gas containing nitrogen to the surface of the substrate. The third step includes feeding a third gas containing hydrogen to the surface of the substrate.

Abstract: In a method of forming a fine pattern, a silicon-oxide-based film is formed directly or by way of another layer on a substrate or on an underlying layer. The silicon-oxide-based film is formed such that nitrogen content of the surface thereof assumes a value of 0.1 atm. % or less. A chemically-amplified photoresist layer is formed on the silicon-oxide-based film. A mask pattern of a mask is transferred onto the chemically-amplified photoresist layer upon exposure through the mask. Thus, there is prevented generation of a tapered corner in a portion of a resist pattern in the vicinity of a boundary area between the resist pattern and a substrate.

Abstract: A method of designing a charged particle beam mask, comprises locating a plurality of identical chip patterns on a charged particle beam mask in which a plurality of subfields that can be transferred at a time are provided vertically and horizontally. The chip patterns have an arrangement pitch that is an integer multiple of the subfield.

Abstract: A method of manufacturing a membrane mask for use in an electron beam exposure apparatus that exposes resist material, comprises manufacturing the membrane mask. A membrane thickness is determined so that an operation time that the electron beam exposure apparatus spends in exposing the resist material to form a predetermined pattern using the membrane mask is comparable to or less than an operation time that the electron beam exposure apparatus spends in exposing the resist material to form the predetermined pattern using complementary masks.

Abstract: In a method for manufacturing a semiconductor device, gate insulation films and gate electrodes are first formed on a substrate. An impurity is implanted into each gate electrode. Next, a first heat treatment is performed to the substrate for diffusing the impurity in the gate electrodes. After the heat treatment, a second heat treatment is performed for releasing stress generated in the substrate in the first heat-treatment. Thereafter, an impurity is implanted into an area to become an implanted region of the substrates using the gate electrodes as masks, and a third heat treatment is performed for activating the impurity implanted.

Abstract: To effectively reduce the dielectric constant of an interlayer insulation film including a low dielectric constant film of a porous structure, and easily realize a practical application of a semiconductor device having an ultrafine and highly reliable Damascene wiring structure. A first interlayer insulation film including a porous first low dielectric constant film is formed on a lower layer wiring, and a first side wall metal is formed on a side wall of a via hole arranged in the first low dielectric constant film, and thereafter a first etching stopper layer is etched and the lower layer wiring is exposed. Then, a via plug is embedded into the via hole. In the same manner, after a second side wall metal is arranged on a side wall of a trench in a second interlayer insulation film including a porous second low dielectric constant film, a second etching stopper layer is etched, and an upper layer wiring that connects to the via plug is formed.

Abstract: A method of performing microfabrication using a hard mask in the manufacture of a semiconductor device having an interlayer dielectric (ILD) film made of low-dielectric constant, K, insulating material is provided. When treating a low-K dielectric film for use in semiconductor integrated circuitry and its underlying etching stopper film, a patterned resist film is used as a mask to etch a hard mask film. Subsequently, the resist pattern is subjected to stripping or “ashing” in the atmosphere of a mixture gas of hydrogen (H2) and helium (He) at a temperature higher than 200° C. under a pressure of about 1 Torr. With this procedure, microfabrication relying upon the hard mask less in facet is achievable during its subsequent etching of the low-K dielectric film, without damaging the hard mask film upon removal of the resist.

Abstract: A gate insulating film and a gate electrode are formed on a silicon substrate. The gate insulating film contains at least hafnium, oxygen, fluorine, and nitrogen. The fluorine concentration is high in the vicinity of an interface with the silicon substrate and progressively decreases with decreasing distance from the gate electrode. The nitrogen concentration is high in the vicinity of an interface with the gate electrode and progressively decreases with decreasing distance from the silicon substrate. The fluorine concentration in the vicinity of the interface with the silicon substrate is preferably 1×1019 cm?3 or more. The nitrogen concentration in the vicinity of the interface with the gate electrode is preferably 1×1020 cm?3 or more.

Abstract: A semiconductor device comprises a semiconductor layer; a stacked body; and an electrode pad provided on the stacked body. The stacked body is provided on the semiconductor layer and has a plurality of stacked layers. The electrode pad is provided on the stacked body. The stacked body has a subpad region that is located below the electrode pad and an extrapad region that is not located below the electrode pad, and any portion made of insulating material in the electrode subpad region except a contact plug layer directly above the semiconductor layer in the stacked body is surrounded by a metal interconnect having a closed structure in the same layer.

Abstract: An atomic layer deposition (ALD) apparatus capable of forming a conformal ultrathin-film layer with enhanced step coverage is disclosed. The apparatus includes an ALD reactor supporting therein a wafer, and a main pipe coupled thereto for constant supply of a carrier gas. This pipe has two parallel branch pipes. Raw material sources are connected by three-way valves to one branch pipe through separate pipes, respectively. Similarly, oxidant/reducer sources are coupled by three-way valves to the other branch pipe via independent pipes. ALD works by introducing one reactant gas at a time into the reactor while being combined with the carrier gas. The gas is “chemisorped” onto the wafer surface, creating a monolayer deposited. During the supply of a presently selected material gas from its source to a corresponding branch pipe, this gas passes through its own pipe independently of the others. An ALD method is also disclosed.

Abstract: A wet etching apparatus comprises a stage for fixing a substrate having a major surface covered with a film to be etched, a rotation mechanism for rotating the stage, a rotation controller for controlling rotation operation by the rotation mechanism, an ultraviolet irradiation unit having a light source for irradiating a portion of the major surface of the substrate with ultraviolet radiation, and an etching solution supply unit for supplying etching solution to the major surface of the substrate. The entire surface of the substrate can be irradiated with the ultraviolet radiation by a rotation of the stage.

Abstract: In a semiconductor device having a first transistor and a second transistor, the first transistor includes a first gate electrode composed of a first material having a first work function, and a first gate insulating film. The second transistor includes a second gate electrode composed of a second material having a second work function, and a second gate insulating film. The first gate insulating film includes a high-dielectric-constant film, and a first insulating film on the high-dielectric-constant film. In the second gate insulating film, after removing the first gate electrode, the first insulating film on the high-dielectric-constant film is removed.

Abstract: Disclosed is a method of removing resist preventing increase of dielectric constant of low permittivity insulating films and preventing remains of resist. Using a resist mask, a protection insulating film, a MSQ film, and a silicon oxide film composing an ILD are RIE dry etched sequentially, and a via is formed on the surface of a substrate for processing reaching the diffusion layer on the substrate for processing. Subsequent process consists of; removing a modified layer formed on the substrate for processing surface because of prior etching using plasma gas by plasma excitation of NH3 gas, and another etching for complete removal of the resist mask by irradiation of hydrogen active species created by hydrogen gas and inert gas, of which example is helium gas or argon gas.

Abstract: In resist removal using hydrogen gas, the specific dielectric constant of an insulating film of a low dielectric constant can be reduced and the resist removal speed can be increased. A wafer is loaded on a rotary table in a chamber, and hydrogen mixed gas is introduced into a discharge tube from a gas introduction port, and a ? wave is supplied into the discharge tube via a waveguide, and the mixed gas is excited by plasma, and a hydrogen active species is generated. And, a neutral radical (hydrogen radical) of hydrogen atoms or hydrogen molecules is introduced into the chamber from a gas transport pipe and a resist mask on the surface of the wafer is removed. Here, by a substrate heating system for heating the rotary table and controlling the temperature, the temperature of the wafer is set within the range from 200° C. to 400° C. The processed gas after resist removal is ejected from the chamber through a gas ejection port by an exhaust system.

Abstract: An element isolation dielectric film is formed around device regions in a silicon substrate. The device regions are an n-type diffusion region, a p-type diffusion region, a p-type extension region, an n-type extension region, a p-type source/drain region, an n-type source/drain region, and a nickel silicide film. Each gate dielectric film includes a silicon oxide film and a hafnium silicate nitride film. The n-type gate electrode includes an n-type silicon film and a nickel silicide film, and the p-type gate electrode includes a nickel silicide film. The hafnium silicate nitride films are not on the sidewalls of the gate electrodes.

Abstract: The group creation part divides n ion particles into groups of a group G1, a group G2, . . . , and a group Gk. The individual area setting part sets an initial condition calculation area 1a, as an individual area of the group G1, and makes the calculation part calculate movement of the ion particle. Then, one by one, the individual area setting part sets an individual area of a group Gi+1, based on a range Rp, a dispersion ?L, etc. indicating a calculation result of an ion particle belonging to the group G1. Further, the individual area setting part implants an ion particle belonging to the group Gi+1 into the individual area of the group Gi+1 and makes the calculation part calculate movement of the implanted ion particle.

Abstract: A phase shift mask comprises a transparent substrate and a light shielding film. The transparent substrate has two regions that transmit exposure light. The exposure light transmitted through one region having a phase that is inverted in a recessed portion formed in the other region. The light shielding film shields the exposure light. The light shielding film is formed on the transparent substrate with a plurality of film thicknesses and has an edge that does not hang over the recessed portion.

Abstract: A substrate-container measuring device has a kinematic plate 10 having securing pins 12 provided at positions defined by the SEMI standards. There is provided an optical distance-measuring sensor 14, in which a relative position between the optical distance-measuring sensor 14 and the kinematic plate 10 is fixed. A substrate-container measuring jig 20 is placed on the kinematic plate 10. The substrate-container measuring jig 20 has a base plate 22 to be placed on the kinematic plate 10, and a slide plate 24 that is slidable over the base plate 22. The base plate 22 has a group of grooves which uniquely determine a relative position between the base plate 22 and the kinematic plate 10 as a result of being fitted with the corresponding securing pins 12.

Abstract: A method of forming a silicon nitride film comprises: forming a silicon nitride film by applying first gas containing silicon and nitrogen and second gas containing nitrogen and hydrogen to catalyst heated in a reduced pressure atmosphere. A method of manufacturing a semiconductor device comprising the steps of: forming a silicon nitride film by the method as claimed in claim 1 on a substrate having the semiconductor layer, a gate insulation film selectively provided on a principal surface of the semiconductor layer, and a gate electrode provided on the gate insulation film; and removing the silicon nitride film on the semiconductor layer and the gate electrode and leaving a sidewall comprising the silicon nitride film on a side surface of the gate insulation film and the gate electrode by etching the silicon nitride film in a direction generally normal to the principal surface of the semiconductor layer.