Abstract: An apparatus and method is disclosed that allows for the arranging in a three dimensional array semiconductor chips on a circuit board. A unique chip carrier is disclosed on which any IC chip can be positioned on above the other on a circuit board. Additionally, the carrier allows for the testing of IC chips on the carrier and underneath it without having to remove the carrier and chips from the system even if they are of the BGA or CSP type. The carrier includes exposed test points to allow an on site test.

Abstract: The present invention relates to circuit boards with radially arrayed components. One specific embodiment is a memory circuit board with memory components, such as, for example, DRAM chips, radially arrayed around a central point. The present invention also relates to stacking and connecting multiple circuit boards with radially arrayed components. Another embodiment of the invention involves methods of preparing radially arrayed components on a circuit board module with substantially equidistant paths to the components.

Abstract: An improved multi-chip module includes a circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes multiple IC packages, which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the circuit board. A variety of package carriers are used to create a number of different modules. One type of package carrier has a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. At least one IC package is surface mounted on each major planar surface, by interconnecting the connection elements, or leads, of the package with the contact pads on the planar surface, to form the IC package unit. Another type of package carrier substrate has a multiple recesses for back-to-back surface mounting of the IC packages. The package also includes in various versions heat sinks.

Abstract: A method and apparatus for fabricating a three dimensional array of semiconductor chips is disclosed. The method uses a multiple step fabrication process that automates the surface mounting of semiconductor chips with unique chip carriers to achieve the three dimensional array of chips. The method can include the steps of depositing solder on one or more chip modules, placing and interconnecting low-cost components on the chip modules, and storing the preprocessed chip modules in pallets or in a tape and reel. Later these chip carriers may then be mounted on a circuit board, possibly over; for example, low and/or high cost components and then populated with low and/or high cost components. The apparatus includes a unique stackable chip module pallet and print fixture pedestal.

Abstract: A system for populating a three dimensional array of semiconductor chips is disclosed. The system facilitates the surface mounting of semiconductor chips with chip carriers to achieve the three dimensional array of chips. The system includes a chip carrier pallet that holds and moves the chip carriers for the automatic assembly of a circuit board. The system also may include a print fixture pedestal that works in combination with the chip carrier pallet to position chip carriers for automatic deposition of solder on a multitude of carriers at once, and then position them for addition to a circuit board.

Abstract: A method and apparatus for fabricating a three dimensional array of semiconductor chips is disclosed. The method uses a multiple step fabrication process that automates the surface mounting of semiconductor chips with unique chip carriers to achieve the three dimensional array of chips. The method includes a step of depositing solder on a multitude of chip carriers at one time, placing the chip carriers with chips on a printed circuit board and then running the board with chips and carriers arranged in a three dimensional array through a single reflow oven to complete a single reflow process to permanently connect all of the components. The apparatus includes a unique chip carrier pallet and print fixture pedestal that work in combination to position the chip carriers for the automatic deposition of solder on a multitude of carriers at once and then position them for addition to the circuit board.

Abstract: An apparatus and method is disclosed that allows for the arranging in a three dimensional array semiconductor chips on a circuit board. A unique chip carrier is disclosed on which any IC chip can be positioned on above the other on a circuit board. Additionally, the carrier allows for the testing of IC chips on the carrier and underneath it without having to remove the carrier and chips from the system even if they are of the BGA or CSP type. The carrier includes exposed test points to allow an on site test.

Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. Several different variations of the chip module are disclosed.

Abstract: An improved multi-chip module includes a circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes multiple IC packages, which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the circuit board. A variety of package carriers are used to create a number of different modules. One type of package carrier has a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. At least one IC package is surface mounted on each major planar surface, by interconnecting the connection elements, or leads, of the package with the contact pads on the planar surface, to form the IC package unit. Another type of package carrier substrate has a multiple recesses for back-to-back surface mounting of the IC packages. The IC packages may be in contact with opposite sides of a heat sink layer embedded within the carrier substrate.

Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. A second primary embodiment of the invention utilizes a carrier substrate which has a pair of recesses for back-to-back surface mounting of the IC package pair. The two IC packages may be in contact with opposite sides of a heat sink layer embedded within the carrier substrate.

Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. A second primary embodiment of the invention utilizes a carrier substrate which has a pair of recesses for back-to-back surface mounting of the IC package pair. The two IC packages may be in contact with opposite sides of a heat sink layer embedded within the carrier substrate.

Abstract: A circuit board assembly having integrated circuit packages vertically arranged three dimensionally is used to increase electronic component density without increasing the size of the circuit board. For a preferred embodiment of the circuit board assembly, the printed circuit board has at least one primary mounting pad array affixed thereto, each pad of the array having first and second portions. Each lead of a first integrated circuit package is conductively bonded to the first portion of a different mounting pad of said primary array. A package carrier having a plurality of carrier leads attached thereto and a secondary mounting pad array on an upper surface thereof, covers the first package. Each lead of the carrier is coupled to a different pad of the secondary array and is also conductively bonded to the second portion of a different mounting pad of the primary array. Each lead of a second integrated circuit package is conductively bonded to a different mounting pad of the secondary mounting pad array.