Abstract: An apparatus includes an on timer configured to determine an on time of a high-side switch of a step-down power converter, an offset current control stage configured to convert a voltage difference between a compensation signal and a predetermined reference into a current difference, a current comparison stage configured to amplify a sensed current signal, and a PWM comparator having inputs coupled to two outputs of the current comparison stage and two outputs of the offset current control stage, wherein during a load transient from a first load level to a second load level and in a first turn-on pulse of the high-side switch, the on timer is disabled so that a current flowing through the step-down power converter reaches the second load level within the first turn-on pulse of the high-side switch.

Abstract: A hybrid power transistor apparatus includes a first switching element comprising a first number of transistor cells connected in parallel between a first terminal and a second terminal of the apparatus, wherein gates of the first number of transistor cells are connected together, and the gates of the first number of transistor cells are connected to an output of a first gate drive circuit, and a second switching element comprising a second number of transistor cells connected in parallel between the first terminal and the second terminal of the apparatus, wherein gates of the second number of transistor cells are connected together, and the gates of the second number of transistor cells are connected to an output of a second gate drive circuit, and wherein a delay is placed between the output of the first gate drive circuit and the output of the second gate drive circuit.

Abstract: An apparatus includes a current sensing gain stage comprising a first leg and a second leg, wherein each leg comprises a plurality of transistors connected in series, a first track stage configured to receive a first current sensing signal, wherein the first track stage comprises a first bias transistor configured to provide a first range of headroom for the first leg of the current sensing gain stage, and a second track stage configured to receive a second current sensing signal, wherein the second track stage comprises a second bias transistor configured to provide a second range of headroom for the second leg of the current sensing gain stage.

Abstract: A hybrid power transistor apparatus includes a first switching element comprising a first number of transistor cells connected in parallel between a first terminal and a second terminal of the apparatus, wherein gates of the first number of transistor cells are connected together, and the gates of the first number of transistor cells are connected to an output of a first gate drive circuit, and a second switching element comprising a second number of transistor cells connected in parallel between the first terminal and the second terminal of the apparatus, wherein gates of the second number of transistor cells are connected together, and the gates of the second number of transistor cells are connected to an output of a second gate drive circuit, and wherein a delay is placed between the output of the first gate drive circuit and the output of the second gate drive circuit.

Abstract: An ESD protection apparatus includes a first clamping device and a second clamping device connected in series between a bias voltage bus and ground, and a switch coupled between an input/output pad and a common node of the first clamping device and the second clamping device, wherein the switch is configured such that before a bias voltage on the bias voltage bus has been established, a leakage current flowing through the first clamping device is reduced.

Abstract: An apparatus includes a wide range differential pair configured to operate at a low voltage level through reducing bias currents in a startup process of a power converter, and operate at a high voltage level through configuring detected voltages to bias the wide range differential pair, a reference circuit configured to regulate a current flowing through the power converter through the wide range differential pair, and a low voltage circuit configured to convert differential currents generated by the wide range differential pair into a control voltage for regulating the current flowing through the power converter.

Abstract: An apparatus includes a high gain input stage configured as an integrator in a successive approximation register (SAR) analog-to-digital converter (ADC), a clamping and filtering stage configured to clamp a voltage on a high impedance node to a predetermined level approximately equal to a diode voltage drop in a clamping mode of an SAR cycle, and a decision-making stage connected to an output of the clamping and filtering stage.