Abstract: An interconnection network architecture which provides an interconnection network which is especially useful for FPGAs is described. Based upon Benes networks, the resulting network interconnect is rearrangeable so that routing between logic cell terminals is guaranteed. Upper limits on time delays for the network interconnect are defined and pipelining for high speed operation is easily implemented. The described network interconnect offers flexibility so that many design options are presented to best suit the desired application.

Abstract: A programmable interface for FPGA cores embedded in an integrated circuit. The interface has an interconnect multiplexer (which includes demultiplexers) connected to the FPGA core and other elements of the integrated circuit. A control portion of the interface provides selection control bits to the interconnect multiplexer to make the desired connection configuration. Programmable latches in the control portion hold the selection bits which are loaded into the latches at the same time configuration bits are loaded into the integrated circuit to program the FPGA core. Alternatively, the control portion can be implemented by another FPGA core which is configured as a state machine to generate the selection control bits.

Abstract: A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.

Abstract: A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.

Abstract: An interconnection network architecture which provides an interconnection network which is especially useful for FPGAs is described. Based upon Benes networks, the resulting network interconnect is rearrangeable so that routing between logic cell terminals is guaranteed. Upper limits on time delays for the network interconnect are defined and pipelining for high speed operation is easily implemented. The described network interconnect offers flexibility so that many design options are presented to best suit the desired application.

Abstract: A segmentation architecture for wiring segments which provides interconnections for a gate array integrated circuit is described. Programming is provided by selectable vias between wiring segments and to the semiconductor substrate surface. The wiring segments of two interconnection layers are arranged in two directions and a programmable buffer can drive signals in a selectable direction depending upon how the via contacts are made to the buffer by the wiring segments carrying the buffer signals.

Abstract: An interconnection network architecture which provides an interconnection network which is especially useful for FPGAs is described. Based upon Benes networks, the resulting network interconnect is rearrangeable so that routing between logic cell terminals is guaranteed. Upper limits on time delays for the network interconnect are defined and pipelining for high speed operation is easily implemented. The described network interconnect offers flexibility so that many design options are presented to best suit the desired application.

Abstract: This invention consists of a hierarchical multiplexer-based interconnect architecture and is applicable to Field Programmable Gate Arrays, multi-processors, and other applications that require configurable interconnect networks. In place of traditional pass transistors or gates, multiplexers are used and the interconnect architecture is based upon hiearchical interconnection units. Bounded and predictable routing delays, compact configuration memory requirements, non-destructive operation in noisy environments, uniform building blocks and connections for automatic generation, scalability to thousands of interconnected elements, and high routability even under high resource utilization are obtained.

Abstract: A way of protecting the configuration bits of the user of a configurable integrated circuit is described. The user-configurable integrated circuit has a decryption circuit block which decrypts configuration bits which have been encrypted by a plurality of encryption keys corresponding to a plurality of corresponding decryption keys for programming the integrated circuit into a desired configuration. The decryption circuit block receives the plurality of decryption keys from a corresponding plurality of decryption key circuits, at least one of which is embedded in the integrated circuit so as to prevent accessibility of the decryption key. Other decryption key circuits may be part of the integrated circuit or off-chip for accessibility of their decryption keys for ready identification of their owners; still other decryption key circuits may be embedded in the integrated circuit for inaccessibility.

Abstract: An interconnection network architecture which provides an interconnection network which is especially useful for FPGAs is described. Based upon Benes networks, the resulting network interconnect is rearrangeable so that routing between logic cell terminals is guaranteed. Upper limits on time delays for the network interconnect are defined and pipelining for high speed operation is easily implemented. The described network interconnect offers flexibility so that many design options are presented to best suit the desired application.