Abstract: An analog bias current optimization circuitry in a transceiver of a data communication system is capable of controlling the amount of a bias current of each of analog circuits. The analog bias current optimization circuitry generates a signal pattern which is sent to the analog circuits, such as TX-D/A converter, driver, RX-A/D converter, etc., and evaluates the signal quality of the analog circuits. Based on the evaluated signal quality, a bias current to each of the analog circuits is adjusted. A margin may be added to the bias current to ensure the signal quality in case there is a change in power supply voltage and/or temperature. One method of evaluating the signal quality of the analog circuits is to evaluate the residual echo of the output of an echo canceller (EC). Another method is to evaluate a signal error in a decision feedback equalizer (DFE). A further method is to evaluate a harmonic distortion at the output of a filter.

Abstract: A phase-locked loop circuit for providing a tightly controlled capture range for locking an output signal to a data signal, while also providing a wide frequency capture range for initially pulling the output signal within this narrow, predetermined frequency range. The apparatus detects a frequency difference between at least one reference signal and an output signal, and generates a frequency error signal in response to the frequency difference. A phase difference is detected between a received input signal and the output signal, and a phase error signal is generated in response to the phase difference. The frequency error signal and the phase error signal are combined to control the frequency of the output signal by controlling an input-controlled oscillator.