Abstract: A PCI card comprises upper and lower surfaces; a mounting hole defining first and second holes, the first hole having a larger diameter than the second hole; a stud that is inserted into the mounting hole and flushed to the upper surface; and a port connector provided on the stud to minimize space consumption. The first and second holes are concentric circles. Alternatively, the first and second holes are not perfect circles.

Abstract: A PCI card comprises upper and lower surfaces; a mounting hole defining first and second holes, the first hole having a larger diameter than the second hole; a stud that is inserted into the mounting hole and flushed to the upper surface; and a port connector provided on the stud to minimize space consumption. The first and second holes are concentric circles. Alternatively, the first and second holes are not perfect circles.

Abstract: A PCI card comprises upper and lower surfaces; a mounting hole defining first and second holes, the first hole having a larger diameter than the second hole; a stud that is inserted into the mounting hole and flushed to the upper surface; and a port connector provided on the stud to minimize space consumption. The first and second holes are concentric circles. Alternatively, the first and second holes are not perfect circles.

Abstract: Packets received over a network are routed using a packet engine of the invention based on information contained in layer 4 or above. The information for switching is contained in the header information of the packet. Based on this higher level information, the packet engine may drop the packet, redirect the packet, load balance the packet, perform bandwidth provisioning (e.g., limit the speed of a connection), or adjust quality of service (e.g., change priority or rearrange a queue of packets to be handled), or combinations of these.

Abstract: The present invention provides a speculatively loaded memory for use in a data processing system. The present invention may include a memory block including rows each identified by an address. A first register may store a first address of the memory block and a second register may store a second address of the memory block. A control circuit may be coupled to the first and second registers, and may receive control signals. The control circuit causes contents of the first register to be stored into the second register in response to a first state of the control signals, and the control circuit causes contents of the second register to be stored into the first register in response to a second state of the control signals.

Abstract: A memory system includes a memory array for storing a plurality of data elements, the memory array comprising a plurality of memory blocks. In one embodiment, the data element are tag string data. The memory system may also include a comparator unit coupled to receive a memory block output and an input signal, wherein when the memory block output matches the input signal, the memory system transmits a match signal and a code word on a result bus. In one embodiment, data elements are stored as fragments in different portions of the memory array. The input signal may be received as fragments and compared to the data elements over different time periods. In one embodiment, the present invention provides a memory lookup system and method that supports multiple protocols.