Abstract: A first stage circuit for a pipeline ADC first stage combines the functions of an input sample-and-hold-plus-amplifier (SHA) stage, and the functions of the first analog-to-digital conversion stage of an ADC, including a multiplying DAC (MDAC), stage-flash ADC (SFADC) comparators, and residue opamp (RAMP). The ADC first stage is duplicated, inputs and outputs are connected, and an autozero circuit using a switched-capacitor filter feedback loop controls the RAMP bias circuitry to reduce 1/f noise and DC offsets. The sampling capacitors may be connected to the ADC input for one full sample clock time period and are disconnected from the analog input period before connecting the sampling capacitors to an amplifier voltage output or voltage reference, thereby sampling the input and allowing sufficient time for the SFADC comparators to resolve and control the MDAC capacitor settings with a low metastability error rate.

Abstract: A monolithic integrated circuit amplifier has a gain stage and a buffer stage. The buffer stage includes an output stage and two separate voltage supplies, the second of which has a greater magnitude than the first. Switching circuitry is included that is connected to the output stage via a regulator bus. When an output demand voltage is less than a switch-over threshold, current to the output stage is provided substantially from the first voltage supply; when the output demand voltage is greater than the switch-over threshold, current to the output stage is provided substantially from the second voltage supply. Collector voltage at the output stage is dynamically controlled to be greater than the emitter voltage by a difference voltage that increases proportionally as output voltage increases above the switch-over threshold. This difference voltage is commonly referred to as “headroom.

Abstract: In its broadest terms, the invention is an electrostatically shielded and resistively insulated high-value resistor that is implemented using a CMOS resistive sealing layer of a larger CMOS device. In particular, the IC resistor according to the invention uses a substantially continuous, resistive layer to electrically connect the resistor input and output electrodes, which are formed as portions of a top metal layer. The resistive layer itself forms a resistive electrical path between the input and output, isolation of the resistor from other components on the same integrated circuit being provided without patterning of the resistive layer. An output ring portion of the top metal layer is electrically connected to the output electrode and surrounds the input electrode. A grounded shield ring portion of the top metal layer is also preferably included. The shield ring surrounds the output ring portion and forms a first electrostatic shield for the resistor.

Abstract: A digital-to-analog converter (DAC) includes separate converter segments for converting the most significant bits (MSB's) and next-most-significant bits (NSB's) of a digital input word. The MSB's are converted in a thermometer-encoded capacitive DAC (CDAC), in which the MSB's are decoded and used to control the state of CDAC switches, which connect any of a plurality of CADC reference voltages, through respective unit capacitors, to the DAC output. The NSB's are converted in a preferably binary encoded resistive DAC (RDAC), in which two separate sets (“A” and “B”) of RDAC switches selectively connect a plurality of RDAC reference voltages to respective A and B RDAC output buses. Control circuitry is included to decode and apply the MSB's as state control signals to the CDAC switches on each clock cycle. The NSB's are also decoded and applied as control signals, but on alternate clock cycles, to the A and B RDAC switch sets.