Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.

Abstract: A method and apparatus is disclosed for identifying a block being stored within flash memory devices using a cluster address for each block, the block being selectively erasable and having one or more sectors, the cluster address being stored in one of the sectors of the block. In an alternative embodiment, the cluster address is stored in at least two different sectors within the same block for ensuring that the information last written to the block is valid. Further disclosed is a novel way to use a defect flag for each block stored within the flash memory device for efficiently identifying non-defective blocks upon system power-up.

Abstract: In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored.

Abstract: An improved compact flash memory card system includes an improved compact flash memory card desktop adapter and an improved compact flash memory card. The improved compact flash memory card desktop adapter utilizes a fifty pin socket to interface with the compact flash memory card. The desktop adapter also utilizes a plug adapter to interface with a computer. For more efficient communication between the improved compact flash memory card and the computer, the improved desktop adapter adopts the universal serial bus architecture. The improved compact flash memory card utilizes a fifty pin connection to interface with a computer through an interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial bus mode, PCMCIA mode, and ATA IDE mode. Each of these modes of operation require different protocols.

Abstract: In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored.

Abstract: In accordance with an embodiment of the present invention, a solid state storage system and method is disclosed for reducing the number of write operations when re-writing a block of information that has been previously written by a host. The system includes a controller coupled to a host and a nonvolatile memory unit for controlling reading and writing of information organized in sectors from and to the nonvolatile memory unit, as commanded by the host. The controller maintains mapping of the sector information in an LUT stored in volatile memory the contents of which are lost if power is lost. Through the use of an address value and flag information maintained within each of the blocks of the nonvolatile memory unit, a block is re-written using a different number of write operations in various alternative embodiments of the present invention.

Abstract: A device is disclosed for storing mapping information for mapping a logical block address identifying a block being accessed by a host to a physical block address, identifying a free area of nonvolatile memory, the block being selectively erasable and having one or more sectors that may be individually moved. The mapping information including a virtual physical block address for identifying an "original" location, within the nonvolatile memory, wherein a block is stored and a moved virtual physical block address for identifying a "moved" location, within the nonvolatile memory, wherein one or more sectors of the stored block are moved. The mapping information further including status information for use of the "original" physical block address and the "moved" physical block address and for providing information regarding "moved" sectors within the block being accessed.

Abstract: An embodiment of the present invention includes a nonvolatile memory system for storing sector information in storage locations within nonvolatile memory organized into blocks, a plurality of blocks defining a super block and each block having a predetermined plurality of sectors. The nonvolatile memory system includes a controller for shifting sector information to a first and a second block of a particular super block and writing sector information to the first block of the particular super block, wherein shifting to the second block occurs entirely during the writing to the first block thereby decreasing the time required to perform write operations to blocks and increasing overall system performance.

Abstract: In accordance with an embodiment of the present invention, a method and apparatus is disclosed for use in a digital system having a host coupled to at least two nonvolatile memory devices. The host stores digital information in the nonvolatile memory devices and reads the stored digital information from the nonvolatile memory devices. The memory devices are organized into blocks of sectors of information. The method is for erasing digital information stored in the blocks of the nonvolatile memory devices and comprises assigning a predetermined number of blocks, in sequential order, to each of the nonvolatile memory devices, each block having a predetermined number of sectors.

Abstract: A method and apparatus is disclosed for identifying a block being stored within flash memory devices using a cluster address for each block, the block being selectively erasable and having one or more sectors, the cluster address being stored in one of the sectors of the block. In an alternative embodiment, the cluster address is stored in at least two different sectors within the same block for ensuring that the information last written to the block is valid. Further disclosed is a novel way to use a defect flag for each block stored within the flash memory device for efficiently identifying non-defective blocks upon system power-up.

Abstract: A digital system is disclosed for use with a host, the digital system including a controller and a nonvolatile memory unit having memory locations organized in blocks with each block having a plurality of sectors for storing information provided by the host in the form of non-user data files and user data files, the controller for controlling reading, writing and erasing operations performed on the nonvolatile memory, the host providing to the controller an address, identifying the starting location of the user file to the controller, and a user file identified by a starting sector address for storage within the nonvolatile memory unit. The controller finds a free block within the nonvolatile memory unit that is available for storage of information, and aligns the user file starting address with the beginning of the free block, and stores the user file within the free block starting with the beginning of the free block.

Abstract: In accordance with an embodiment of the present invention, a solid state storage system and method is disclosed for reducing the number of write operations when re-writing a block of information that has been previously written by a host. The system includes a controller coupled to a host and a nonvolatile memory unit for controlling reading and writing of information organized in sectors from and to the nonvolatile memory unit, as commanded by the host. The controller maintains mapping of the sector information in an LUT stored in volatile memory the contents of which are lost if power is lost. Through the use of an address value and flag information maintained within each of the blocks of the nonvolatile memory unit, a block is re-written using a different number of write operations in various alternative embodiments of the present invention.

Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.

Abstract: An oscillator circuit residing internally to a semiconductor device for generating a clock signal for use by digital circuits. The oscillator circuit includes a voltage regulator circuit responsive to frequency selection signals for selecting a predetermined frequency and a supply voltage. The voltage regulator circuit is operative to generate a voltage reference signal having a voltage level being adjusted to compensate for variations due to temperature, process and supply voltage variations. The oscillator circuit further includes a ring oscillator circuit responsive to the voltage reference signal for generating a clock out signal having a particular frequency based upon the voltage level of the voltage reference signal. Wherein the frequency of the clock out signal remains substantially constant despite temperature, process and supply voltage variations in the semiconductor circuit.

Abstract: The present invention includes a digital system having a controller semiconductor device coupled to a host and a nonvolatile memory bank including a plurality of nonvolatile memory devices. The controller transfers information, organized in sectors, with each sector including a user data portion and an overhead portion, between the host and the nonvolatile memory bank and stores and reads two bytes of information relating to the same sector simultaneously within two nonvolatile memory devices. Each nonvolatile memory device is defined by a row of memory locations wherein corresponding rows of at least two semiconductor devices maintain two sectors of information therein with the overhead information relating to the two sectors maintained in one of the memory rows of the nonvolatile memory device.

Abstract: In a digital system having a host, a controller device and at least one flash memory integrated circuit, a method and apparatus for storing location identification information regarding blocks of information within at least one of the flash memory integrated circuits wherein at least two buffers within the at least one of the flash memory integrated circuits are designated as primary and secondary buffers for storing the identification information in the primary buffer until the primary buffer is effectively full and storing additional identification information in the secondary buffer until it is effectively full, swapping buffer designation so that the primary buffer becomes the secondary buffer and the secondary buffer becomes the primary buffer, erasing the effectively-full buffer for re-use and in this manner, continuously swapping storage of identification information between the two buffers.

Abstract: An improved flash memory system includes a flash array, internal buffer, and internal controller. When data is written from a source block to a destination block, the improved flash memory system temporarily holds this data inside the internal buffer within the flash memory system to save the overhead of sequentially transferring the data out of the flash system and then sequentially returning the data back to the system. Alternatively, the data can be read and concurrently programmed onto the destination block without being written into an internal latch. In use, this improved flash memory system simply transfers the data to be rewritten from the flash array either directly or to the internal buffer. This improved flash memory system locates a new address within this same flash array.

Abstract: A method for increasing the data reliability of a flash memory device without compromising compatibility with existing memory products or an existing memory format makes only minor modifications to the flash memory device. Inside the flash memory device which supports a low power Error Correcting Code known as Hamming Code, the flash memory cells are divided into groups called blocks. Each block is further divided into units called sectors. Each sector is partioned into well defined areas of bits including: SCRATCH DATA, DATA STATUS, and BLOCK STATUS. According to the method, the bits in DATA STATUS and BLOCK STATUS are modified within the specifications of the existing memory format so they can serve as indicators of the increased data reliability capacity of the flash memory device but continue to carry out the function allocated by the existing memory format. Additionally, the SCRATCH DATA is converted into a repository for the data reliability bits for a high power Error Correcting Code (HP ECC).

Abstract: In accordance with an embodiment of the present invention, a controller device is disclosed for use in a digital system having a host and nonvolatile memory devices. The controller device is coupled to the host and at least two nonvolatile memory devices. The host stores digital information in the nonvolatile memory unit and reads the stored digital information from the nonvolatile memory unit under the direction of the controller, the memory unit being organized into blocks of sectors of information. The controller device erases the digital information stored in the blocks of the nonvolatile memory devices in-parallel form. The controller device includes a space manager circuit responsive to address information from the host and operative to read, write or erase information in the nonvolatile memory unit based upon the host address information.

Abstract: The present invention includes a circuit for deriving a reference signal having a reference voltage from a system voltage source having a system voltage level and for regulating the reference voltage level. The circuit includes an output sub-circuit, a reference generator sub-circuit, a regulator sub-circuit, a translator sub-circuit, and a low pass filter sub-circuit. The output sub-circuit, which is coupled to the system voltage source, is responsive to a voltage control signal, and is operative to generate the reference signal wherein the reference voltage level is less than or equal to the system voltage level. The reference generator sub-circuit is responsive to the reference signal and is operative to generate a prime voltage level which remains substantially unaffected by fabrication process variations, temperature variations and variations in the reference signal.