Patents Assigned to LFOUNDRY S.R.L.
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Patent number: 12119412Abstract: A semiconductor vertical Schottky diode device, having: a substrate of semiconductor material, with a front surface and a back surface; a lightly doped region formed in a surface portion of the substrate facing the front surface, having a first conductivity type; a first electrode formed on the lightly doped region on the front surface of the substrate, to establish a Schottky contact; a highly doped region at the back surface of the substrate, in contact with the lightly doped region and having the first conductivity type; and a second electrode electrically in contact with the highly doped region, on the back surface of the substrate, to establish an Ohmic contact.Type: GrantFiled: September 20, 2019Date of Patent: October 15, 2024Assignee: LFOUNDRY S.R.L.Inventors: Carsten Schmidt, Gerhard Spitzlsperger
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Patent number: 12048166Abstract: A Hall integrated circuit including a vertical Hall element, having a first wafer and a second wafer, the second wafer including a CMOS substrate integrating a CMOS processing circuit coupled to the vertical Hall element and a stack of dielectric layers, and the first wafer including a Hall-sensor layer having a first surface and a second surface, the first and second wafers being bonded with the interposition of a dielectric layer arranged above the first surface of the Hall-sensor layer. The vertical Hall element has: at least a first Hall terminal; at least a second Hall terminal; a deep trench isolation ring extending through the Hall-sensor layer from the first surface to the second surface and enclosing and isolating a Hall sensor region of the Hall-sensor layer; and a first and a second conductive structures electrically connected to respective contact pads embedded in the stack of the second wafer.Type: GrantFiled: November 21, 2019Date of Patent: July 23, 2024Assignee: LFOUNDRY S.R.L.Inventors: Carsten Schmidt, Mario Blasini, Gerhard Spitzlsperger, Alessandro Montagna
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Patent number: 11127776Abstract: A method to perform hybrid bonding of two semiconductor wafers without using a dedicated tool for thermo-compression is disclosed. According to the herein disclosed technique, the semiconductor wafers to be bonded together may be placed in an oven simply staying one upon the other without applying any additional compression between them besides their own weight. This outstanding result has been attained using of a particular type of thermosetting materials, namely siloxane polymers of the type that shrink when cured. Among these siloxane polymers, the siloxane polymers of the type SC-480, siloxane polymers of the series SC-200, SC-300, SC-400, SC-500, SC-700, SC-800 and mixtures thereof are particularly suitable.Type: GrantFiled: May 17, 2018Date of Patent: September 21, 2021Assignee: LFOUNDRY S.R.L.Inventors: Giovanni De Amicis, Andrea Del Monte, Onorato Di Cola
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Patent number: 11081614Abstract: This disclosure provides a semiconductor sensor of ionizing radiation and/or ionizing particles with a backside bias electrode and a backside junction for completely depleting the semiconductor substrate up to carrier collection regions each connected to a respective collection electrode of carriers generated by ionization in the substrate. Differently from prior sensors, the sensor of this disclosure has an intermediate semiconductor layer formed upon the substrate, having a greater doping concentration than the doping concentration of the substrate and a doping of a same type. In this intermediate layer, buried doped regions of opposite type one separated from the other are formed for shielding superficial regions in which readout circuits are defined.Type: GrantFiled: October 22, 2018Date of Patent: August 3, 2021Assignee: LFOUNDRY S.R.L.Inventors: Angelo Rivetti, Lucio Pancheri, Piero Giubilato, Manuel Dionisio Da Rocha Rolo, Giovanni Margutti, Onorato Di Cola
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Publication number: 20200328321Abstract: This disclosure provides a semiconductor sensor of ionizing radiation and/or ionizing particles with a backside bias electrode and a backside junction for completely depleting the semiconductor substrate up to carrier collection regions each connected to a respective collection electrode of carriers generated by ionization in the substrate. Differently from prior sensors, the sensor of this disclosure has an intermediate semiconductor layer formed upon the substrate, having a greater doping concentration than the doping concentration of the substrate and a doping of a same type. In this intermediate layer, buried doped regions of opposite type one separated from the other are formed for shielding superficial regions in which readout circuits are defined.Type: ApplicationFiled: October 22, 2018Publication date: October 15, 2020Applicant: LFOUNDRY S.R.L.Inventors: Angelo RIVETTI, Lucio PANCHERI, Piero GIUBILATO, Manuel Dionisio DA ROCHA ROLO, Giovanni MARGUTTI, Onorato DI COLA
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Publication number: 20200212086Abstract: A method to perform hybrid bonding of two semiconductor wafers without using a dedicated tool for thermo-compression is disclosed. According to the herein disclosed technique, the semiconductor wafers to be bonded together may be placed in an oven simply staying one upon the other without applying any additional compression between them besides their own weight. This outstanding result has been attained using of a particular type of thermosetting materials, namely siloxane polymers of the type that shrink when cured. Among these siloxane polymers, the siloxane polymers of the type SC-480, siloxane polymers of the series SC-200, SC-300, SC-400, SC-500, SC-700, SC-800 and mixtures thereof are particularly suitable.Type: ApplicationFiled: May 17, 2018Publication date: July 2, 2020Applicant: LFOUNDRY S.R.L.Inventors: Giovanni DE AMICIS, Andrea DEL MONTE, Onorato DI COLA
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Patent number: 10256270Abstract: A method for manufacturing a CMOS image sensor for near infrared detection. The method includes: a) providing a silicon wafer; b) performing a germanium implantation in a portion of a front side of the silicon wafer; c) performing an annealing so as to cause thermal diffusion of implanted germanium species, thereby forming silicon-germanium alloy lattice in a first silicon-germanium region exposed on the front side of the silicon wafer; d) carrying out the steps b) and c) one or more times; and e) forming first photodetector active areas in portions of the first silicon-germanium region downwards extending from the front side of the silicon wafer, wherein said first photodetector active areas are sensitive to both near infrared and visible radiations. The first photodetector active areas are formed also in portions of the silicon wafer extending below said portions of the first silicon-germanium region.Type: GrantFiled: December 30, 2016Date of Patent: April 9, 2019Assignee: LFOUNDRY S.R.L.Inventors: Giovanni Margutti, Andrea Del Monte
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Patent number: 10002836Abstract: A method of fabricating a semiconductor product including processing of a semiconductor wafer from a front surface including structures disposed in the substrate of the wafer adjacent to the front surface and forming a wiring embedded in a dielectric layer disposed on the front surface. The wafer is mounted to a carrier wafer at its front surface so that material can be removed from the backside of the wafer to thin the wafer. Backside processing of the wafer includes forming implantations from the backside, forming deep trenches to isolate the structures from other structures within the wafer, forming a through-silicon via to contact features on the frontside of the wafer, and forming a body contact. Several devices can be generated within the same wafer.Type: GrantFiled: February 27, 2015Date of Patent: June 19, 2018Assignee: LFoundry S.r.l.Inventors: Gerhard Spitzlsperger, Carsten Schmidt
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Publication number: 20160290946Abstract: An integrated gas sensor having a tungsten/tungsten oxide gas sensing element, is provided with: a substrate of semiconductor material; and a structure of interconnection layers, arranged above the substrate and made of a number of stacked conductive layers and dielectric layers. The gas sensing element is integrated within the structure of interconnection layers and at least one electrode is provided within the structure of interconnection layers, electrically connected to the gas sensing element, designed to provide an electric current to the gas sensing element in order to cause heating thereof.Type: ApplicationFiled: November 12, 2014Publication date: October 6, 2016Applicant: LFOUNDRY S.R.L.Inventor: Josep Montanya Silvestre